公开(公告)号：US07084449B2

公开(公告)日：2006-08-01

申请号：US10710146

申请日：2004-06-22

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  David R. Hanson ,  Carl J. Radens

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  David R. Hanson ,  Carl J. Radens

IPC分类号： H01L27/108 ,  H01L29/00

CPC分类号： H01L29/66181 ,  H01L27/1087 ,  H01L27/10894 ,  H01L29/945

摘要： A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface.

摘要翻译： 提供具有主表面的微电子元件，微电子元件包括形成在第一沟槽的侧壁上的第一电容器，第一沟槽从主表面沿向下延伸的方向伸长。 微电子元件还包括形成在第二沟槽的侧壁上的第二电容器，第二沟槽从主表面沿向下延伸的方向伸长，其中第一电容器的顶部设置在距离主表面的第一深度处， 并且第二电容器的顶部设置在距离主表面的第二深度处。

公开(公告)号：US08901664B2

公开(公告)日：2014-12-02

申请号：US13151525

申请日：2011-06-02

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

IPC分类号： H01L27/092 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

摘要翻译： 用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。 施主材料外延地沉积在鳍结构的暴露的侧壁上。 施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。 施主材料被去除，并且从翅片结构形成场效应晶体管。

公开(公告)号：US08268729B2

公开(公告)日：2012-09-18

申请号：US12195691

申请日：2008-08-21

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ying Zhang

IPC分类号： H01L21/302 ,  H01L21/324

CPC分类号： H01L21/30608 ,  H01L29/045 ,  H01L29/66795

摘要： A method for processing a semiconductor fin structure is disclosed. The method includes thermal annealing a fin structure in an ambient containing an isotope of hydrogen. Following the thermal annealing step, the fin structure is etched in a crystal-orientation dependent, self-limiting, manner. The crystal-orientation dependent etch may be selected to be an aqueous solution containing ammonium hydroxide (NH4OH). The completed fin structure has smooth sidewalls and a uniform thickness profile. The fin structure sidewalls are {110} planes.

摘要翻译： 公开了一种半导体鳍片结构的处理方法。 该方法包括在含有氢同位素的环境中对翅片结构进行热退火。 在热退火步骤之后，鳍结构被蚀刻成晶体取向的自限制的方式。 取决于晶体取向的蚀刻可以选择为含有氢氧化铵（NH 4 OH）的水溶液。 完成的翅片结构具有平滑的侧壁和均匀的厚度轮廓。 翅片结构侧壁是{110}平面。

公开(公告)号：US20110204384A1

公开(公告)日：2011-08-25

申请号：US13101267

申请日：2011-05-05

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Toshiharu Furukawa ,  Xuefeng Hua

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Toshiharu Furukawa ,  Xuefeng Hua

IPC分类号： H01L27/12 ,  H01L29/12 ,  G06F17/50 ,  B82Y99/00

CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L29/1079 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

摘要翻译： 公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。 该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。 然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加 凹槽 随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。 还公开了平面FET结构和平面FET的设计结构的实施例。

公开(公告)号：US20110092069A1

公开(公告)日：2011-04-21

申请号：US12582137

申请日：2009-10-20

申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

IPC分类号： H01L21/3205 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76829

摘要： A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

摘要翻译： 形成半导体器件的方法包括：图案化在待蚀刻的均匀半导体器件层上形成的光致抗蚀剂层; 对半导体器件进行注入工艺，该注入工艺根据待均匀半导体器件层内待蚀刻的特征的位置以及在要蚀刻的特征的期望深度选择性地埋入自对准的牺牲蚀刻停止层; 将由图案化的光致抗蚀剂层限定的特征图案蚀刻成均匀的半导体器件层，停止在注入的牺牲蚀刻停止层上; 以及在用填充材料填充蚀刻的特征图案之前去除注入的牺牲蚀刻停止层的剩余部分。

公开(公告)号：US20100210098A1

公开(公告)日：2010-08-19

申请号：US12372174

申请日：2009-02-17

申请人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

发明人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

IPC分类号： H01L21/283

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76829

摘要： A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.

摘要翻译： 一种形成用于半导体器件的触点的方法，所述方法包括在多个栅极叠层之间沉积层间电介质（ILD），其中层间电介质层内的阴影由栅极堆叠之间的空间限定，填充 具有初始填充材料的图案，在栅极堆叠上的电介质上沉积掩模材料，并且选择性地蚀刻填充材料以形成接触孔。 填充材料可以是自组装材料，例如多嵌段共聚物，其中嵌段自由地在密封区内垂直组织，使得嵌段材料的选择性蚀刻将从竖纹中去除垂直组织的块，而是离开 在门区域上至少有一个块。 在另一个实施方案中，填充材料可以是金属，掩蔽材料可以是聚对二甲苯基聚合物。

公开(公告)号：US08525186B2

公开(公告)日：2013-09-03

申请号：US13101267

申请日：2011-05-05

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Toshiharu Furukawa ,  Xuefeng Hua

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Toshiharu Furukawa ,  Xuefeng Hua

IPC分类号： H01L21/00

CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L29/1079 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

摘要翻译： 公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。 该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。 然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加 凹槽 随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。 还公开了平面FET结构和平面FET的设计结构的实施例。

公开(公告)号：US20120280250A1

公开(公告)日：2012-11-08

申请号：US13100589

申请日：2011-05-04

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Sivananda K. Kanakasabapathy ,  Hemant Adhikari

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Sivananda K. Kanakasabapathy ,  Hemant Adhikari

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

摘要： A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.

摘要翻译： 一种制造半导体器件的方法，其包括至少两个翅片结构，其中所述至少两个翅片结构中的一个包括外延形成的原位掺杂的第二源极和漏极区域，其具有存在于鳍的侧壁上的刻面外侧壁 结构体。 在另一个实施例中，本发明还提供一种制造finFET的方法，其包括在鳍结构的侧壁中形成凹槽，并且在形成在鳍结构中的凹槽中外延形成延伸掺杂区域。 还描述了通过上述方法形成的结构。

公开(公告)号：US20110175164A1

公开(公告)日：2011-07-21

申请号：US12689346

申请日：2010-01-19

申请人： Stephen W. Bedell ,  Huiming Bu ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Chun-chen Yeh

发明人： Stephen W. Bedell ,  Huiming Bu ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Chun-chen Yeh

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.

摘要翻译： 一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构 在活跃地区。 在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

公开(公告)号：US20110101455A1

公开(公告)日：2011-05-05

申请号：US12611444

申请日：2009-11-03

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

摘要： A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

摘要翻译： 通过在翅片和栅极堆叠上共同沉积间隔材料并执行成角度的离子杂质来提供具有覆盖形成在衬底上的半导体材料的翅片的一部分的栅极叠层长度上具有基本上均匀分布的间隔物的FinFET 大致平行于栅极堆叠的植入物选择性地仅对沉积在鳍片上的间隔物材料造成损害。 由于由成角度的植入物引起的损伤，翅片上的间隔物材料可以以高选择性蚀刻到栅极堆叠上的间隔物材料。