公开(公告)号：US20080284992A1

公开(公告)日：2008-11-20

申请号：US12168183

申请日：2008-07-07

申请人： Steven J. Holmes ,  Mark C. Hakey ,  David V. Horak ,  James G. Ryan

发明人： Steven J. Holmes ,  Mark C. Hakey ,  David V. Horak ,  James G. Ryan

IPC分类号： G03B27/52

CPC分类号： B01D53/02 ,  B01D2253/102 ,  B01D2253/304 ,  B01J20/20 ,  B01J20/205 ,  B01J20/3242 ,  B82Y30/00 ,  Y10S55/05 ,  Y10S977/742 ,  Y10S977/745 ,  Y10S977/748 ,  Y10S977/75 ,  Y10S977/752

摘要： An exposure system for exposing a photoresist layer on a top surface of a wafer to light. The exposure system including: an environment chamber containing a light source, one or more focusing lenses, a mask holder, a slit and a wafer stage, the light source, all aligned to an optical axis, the wafer stage moveable in two different orthogonal directions orthogonal to the optical axis, the mask holder and the slit moveable in one of the two orthogonal directions; a filter in a sidewall of the environment chamber, the filter including: a filter housing containing chemically active carbon nanotubes, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and means for forcing air or inert gas first through the filter then into the environment chamber and then out of the environment chamber.

摘要翻译： 一种用于将晶片顶表面上的光致抗蚀剂层曝光的曝光系统。 所述曝光系统包括：包含光源，一个或多个聚焦透镜，掩模支架，狭缝和晶片台的环境室，所述光源均与光轴对齐，所述晶片台可沿两个不同的正交方向移动 与所述光轴正交，所述掩模支架和所述狭缝能够在两个正交方向中的一个方向上移动; 所述过滤器包括：包含化学活性碳纳米管的过滤器壳体，所述化学活性碳纳米管包含在碳纳米管上形成的化学活性层或在碳纳米管的侧壁上包含化学反应性基团; 以及首先通过过滤器将空气或惰性气体强制进入环境室然后离开环境室的装置。

公开(公告)号：US06204112B1

公开(公告)日：2001-03-20

申请号：US09236186

申请日：1999-01-22

申请人： Ashima Bhattacharyya Chakravarti ,  Satya Narayan Chakravarti ,  James G. Ryan

发明人： Ashima Bhattacharyya Chakravarti ,  Satya Narayan Chakravarti ,  James G. Ryan

IPC分类号： H01L218242

CPC分类号： H01L27/10861

摘要： A method for forming an integrated circuit device, and the product thereby produced, are disclosed. The disclosed method includes the steps of obtaining a substrate with a patterned gate conductor and cap insulator, forming a dielectric masking layer having at least one opening, and, using the opening in the dielectric masking layer as a mask, forming a trench capacitor which is self-aligned to the cap insulator edge. The method is particularly useful for a producing a DRAM device having a dense array region with self-aligned deep trench storage capacitors connected by buried straps.

摘要翻译： 公开了一种用于形成集成电路器件的方法以及由此产生的产品。 所公开的方法包括以下步骤：获得具有图案化栅极导体和帽绝缘体的衬底，形成具有至少一个开口的电介质掩模层，并且使用电介质掩模层中的开口作为掩模，形成沟槽电容器，其是 自对准到盖绝缘体边缘。 该方法对于制造具有密集阵列区域的DRAM器件特别有用，该DRAM器件具有通过埋置带连接的自对准深沟槽存储电容器。

公开(公告)号：US5972788A

公开(公告)日：1999-10-26

申请号：US651772

申请日：1996-05-22

申请人： James G. Ryan ,  Badih El-Kareh

发明人： James G. Ryan ,  Badih El-Kareh

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/04 ,  H01L27/108 ,  H01L21/4763

CPC分类号： H01L28/40 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  Y10S438/957

摘要： A metal interconnect having a high conductivity and high resistance to metal migration failure is formed of two layers of metal or alloy (such as TI/CuAlSi) with a dielectric interposed therebetween and a connection made between the layers by a conductive material, preferably in the form of a plug or stud formed in an aperture of an inter-level dielectric, at ends of the interconnect. A high precision metal-to-metal capacitor can be formed from the same layers by forming separate connections to each of the layers. The topography of the interconnect (and capacitor) is of reduced severity and facilitates planarization of an overlying inter-level dielectric.

摘要翻译： 具有高导电性和高金属迁移破坏性的金属互连由两层金属或合金（例如TI / CuAlSi）形成，其中介电介质介于两者之间，并且通过导电材料形成在该层之间的连接，优选在 在互连的端部形成在层间电介质的孔中的插头或螺柱的形式。 通过与每个层形成单独的连接，可以从相同的层形成高精度的金属 - 金属电容器。 互连（和电容器）的形状具有降低的严重性，并且有助于覆盖层间电介质的平坦化。

公开(公告)号：US5909044A

公开(公告)日：1999-06-01

申请号：US897176

申请日：1997-07-18

申请人： Ashima Bhattacharyya Chakravarti ,  Satya Narayan Chakravarti ,  James G. Ryan

发明人： Ashima Bhattacharyya Chakravarti ,  Satya Narayan Chakravarti ,  James G. Ryan

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10861

摘要： A method for forming an integrated circuit device, and the product thereby produced, are disclosed. The disclosed method includes the steps of obtaining a substrate with a patterned gate conductor and cap insulator, forming a dielectric masking layer having at least one opening, and, using the opening in the dielectric masking layer as a mask, forming a trench capacitor which is self-aligned to the cap insulator edge. The method is particularly useful for producing a DRAM device having a dense array region with self-aligned deep trench storage capacitors connected by buried straps.

摘要翻译： 公开了一种用于形成集成电路器件的方法以及由此产生的产品。 所公开的方法包括以下步骤：获得具有图案化栅极导体和帽绝缘体的衬底，形成具有至少一个开口的电介质掩模层，并且使用电介质掩模层中的开口作为掩模，形成沟槽电容器，其是 自对准到盖绝缘体边缘。 该方法对于具有密集阵列区域的DRAM器件特别有用，该DRAM器件具有通过埋置带连接的自对准深沟槽存储电容器。

公开(公告)号：US5803654A

公开(公告)日：1998-09-08

申请号：US738771

申请日：1996-10-29

申请人： Arthur L. Spease ,  James G. Ryan ,  Stephen A. Sauer ,  Bernard Driggers ,  William H. Grojean

发明人： Arthur L. Spease ,  James G. Ryan ,  Stephen A. Sauer ,  Bernard Driggers ,  William H. Grojean

IPC分类号： F16L3/22 ,  F16L3/24 ,  F16C1/10

CPC分类号： F16C1/262 ,  F16L3/22 ,  F16L3/24 ,  Y10T403/71 ,  Y10T403/7171 ,  Y10T403/7188 ,  Y10T74/2045

摘要： A control cable and conduit assembly mounting system includes a pair of integrally formed, arcuate, spaced-apart, flexible flanges which substantially encircle a hollow handlebar or frame member. Also included is a post contained between the flanges which extends through a hole formed in the wall of the tubular handlebar or frame member. The post provides axial and rotational position stability and resists displacing forces caused by movement of the control cable or other forces tending to move the control cable along or rotate the conduit around the handlebar or frame member. The flexible flanges maintain the control cable and conduit assembly in a position proximate to the handlebar or frame member. The elimination of the use of screws or fasteners allows for the cable center line to be parallel with the center line of the handlebar or frame member.

摘要翻译： 控制电缆和导管组件安装系统包括一对整体形成的，弓形的间隔开的柔性凸缘，其基本上环绕中空把手或框架构件。 还包括一个位于凸缘之间的柱，其延伸穿过形成在管状把手或框架构件的壁中的孔。 该柱提供轴向和旋转位置稳定性并且抵抗由控制缆索的移动或其它趋向于使控制缆索沿着手柄或框架构件移动或使导管旋转的力的其他力产生的移动力。 柔性凸缘将控制电缆和导管组件保持在靠近把手或框架构件的位置。 消除使用螺钉或紧固件允许电缆中心线与车把或车架构件的中心线平行。

公开(公告)号：US5563105A

公开(公告)日：1996-10-08

申请号：US316302

申请日：1994-09-30

申请人： David M. Dobuzinsky ,  Tetsuo Matsuda ,  Son V. Nguyen ,  James G. Ryan ,  Michael Shapiro

发明人： David M. Dobuzinsky ,  Tetsuo Matsuda ,  Son V. Nguyen ,  James G. Ryan ,  Michael Shapiro

IPC分类号： C23C16/30 ,  C23C16/40 ,  C23C16/505 ,  H01L21/31 ,  H01L21/316

CPC分类号： H01L21/02131 ,  C23C16/401 ,  C23C16/505 ,  H01L21/02274 ,  H01L21/31625

摘要： Fluorine-doped oxide is formed that is resistant to water absorption by the use of two sources of silicon, one being the fluorine precursor and the other being available to react with excess fluorine from the fluorine precursor, thereby reducing the number of fluorine radicals in the layer; the fluorine precursor containing a glass-forming element that combines with the other glass constituents to carry into the gas a diatomic radical containing one atom of fluorine and one atom of the glass-forming element.

摘要翻译： 形成氟掺杂的氧化物，其通过使用两种硅源而具有耐吸水性，一种是氟前体，另一种可与来自氟前体的过量氟反应，从而减少氟原子的数量 层; 含有玻璃形成元素的氟前体与其它玻璃成分结合，将含有一个氟原子和一个玻璃形成元素原子的双原子基团输送到气体中。

公开(公告)号：US5126006A

公开(公告)日：1992-06-30

申请号：US708608

申请日：1991-05-31

申请人： John E. Cronin ,  Paul A. Farrar, Sr. ,  Robert M. Geffken ,  William H. Guthrie ,  Carter W. Kaanta ,  Rosemary A. Previti-Kelly ,  James G. Ryan ,  Ronald R. Uttecht ,  Andrew J. Watts

发明人： John E. Cronin ,  Paul A. Farrar, Sr. ,  Robert M. Geffken ,  William H. Guthrie ,  Carter W. Kaanta ,  Rosemary A. Previti-Kelly ,  James G. Ryan ,  Ronald R. Uttecht ,  Andrew J. Watts

IPC分类号： G03F1/00 ,  G03F7/00

CPC分类号： G03F7/0035 ,  G03F1/50

摘要： A sequence of masking steps reduces the amount of transference of a workpiece among work stations and reduces certain tolerances required for mask alignment in the construction of integrated circuits, and a gray level mask suitable for photolithography. In the integrated circuit, masking layers are developed directly in a wafer for delineating vertical and horizontal portions of an electrically conductive path. The mask is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. Both the wafer and the mask are fabricated by a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist and other ones of the layers. The etches include plasma etch with chloride ions to attack the chromium of the opaque layer, compounds of fluorine to attack the glass layer, and reactive ion etching with oxygen to attack the photoresist structure.

摘要翻译： 一系列掩蔽步骤减少了工件之间工件的移动量，并降低了集成电路结构中掩模对准所需的某些公差以及适用于光刻的灰度级掩模。 在集成电路中，掩模层直接在晶片中显影，用于描绘导电路径的垂直和水平部分。 掩模由透明玻璃基板构成，其支撑具有不同透光率的多层材料。 在仅使用这些水平中的两个的掩模的情况下，一个层可以由通过取代银离子代替在玻璃的结构中使用的碱金属硅酸盐的金属离子而部分透射的玻璃构成。 第二层可以通过金属如铬的构造而变得不透明。 晶片和掩模都通过光致抗蚀剂结构制造，该光致抗蚀剂结构通过光刻掩模在特定区域中被蚀刻，以使得能够选择性地蚀刻具有不同光学透射率的材料层的暴露区域。 各种蚀刻用于选择性蚀刻光致抗蚀剂和其它层。 蚀刻包括用氯离子等离子体蚀刻以侵蚀不透明层的铬，氟的化合物侵蚀玻璃层，以及用氧反应离子蚀刻以侵蚀光致抗蚀剂结构。

公开(公告)号：US5091289A

公开(公告)日：1992-02-25

申请号：US516394

申请日：1990-04-30

申请人： John E. Cronin ,  Carter W. Kaanta ,  Rosemary A. Previti-Kelly ,  James G. Ryan

发明人： John E. Cronin ,  Carter W. Kaanta ,  Rosemary A. Previti-Kelly ,  James G. Ryan

IPC分类号： C08L79/08 ,  H01L21/312 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76828 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L23/5283 ,  H01L2924/0002

摘要： Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate having a conductor pattern. The insulator layers, each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.

公开(公告)号：US5086016A

公开(公告)日：1992-02-04

申请号：US606632

申请日：1990-10-31

申请人： Stephen B. Brodsky ,  Rajiv V. Joshi ,  John S. Lechaton ,  James G. Ryan ,  Dominic J. Schepis

发明人： Stephen B. Brodsky ,  Rajiv V. Joshi ,  John S. Lechaton ,  James G. Ryan ,  Dominic J. Schepis

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/285 ,  H01L21/331 ,  H01L21/60

CPC分类号： H01L21/76897 ,  H01L21/2254 ,  H01L21/28568 ,  H01L29/66272 ,  Y10S148/034 ,  Y10S148/035

摘要： A contact is provided in a self-aligned manner to a doped region a semiconductor substrate by first forming a layer of a transition metal-boride compound over a selected region on the substrate. A layer of a transition metal-nitride compound is formed over the layer of transition metal-boride compound, and the structure is heated to drive dopant from the layer of transition metal-boride compound into the substrate. The transition metal-boride/transition metal nitride layers are patterned to leave a contact to the doped region.

公开(公告)号：US4464701A

公开(公告)日：1984-08-07

申请号：US527454

申请日：1983-08-29

申请人： Stanley Roberts ,  James G. Ryan

发明人： Stanley Roberts ,  James G. Ryan

IPC分类号： H01L27/04 ,  H01G4/10 ,  H01G4/20 ,  H01L21/318 ,  H01L21/822 ,  H01G4/06

CPC分类号： H01G4/20

摘要： An improved method of fabricating a stable high dielectric constant and low leakage dielectric material which includes oxidizing at a temperature of about 600.degree. C. or higher a layer of a mixture of a transition metal nitride and silicon nitride to produce a mixture which includes an oxide of the transition metal and silicon nitride. The initial mixture of transition metal nitride and silicon nitride may be deposited by reactive sputtering techniques or other known deposition techniques on, a semiconductor or an electrically conductive layer, and the thickness of the mixture should be within the range of 3 to 50 nanometers. By depositing an electrically conductive layer on the oxidized mixture, a capacitor having a high dielectric, and low current leakage dielectric medium is provided.

摘要翻译： 一种制造稳定的高介电常数和低泄漏介电材料的改进方法，其包括在约600℃或更高的温度下氧化过渡金属氮化物和氮化硅的混合物的层，以产生包括氧化物 的过渡金属和氮化硅。 过渡金属氮化物和氮化硅的初始混合物可以通过反应溅射技术或其它已知的沉积技术沉积在半导体或导电层上，并且混合物的厚度应在3至50纳米的范围内。 通过在氧化的混合物上沉积导电层，提供具有高电介质和低电流泄漏电介质的电容器。