公开(公告)号：US5732010A

公开(公告)日：1998-03-24

申请号：US771434

申请日：1996-12-20

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe

IPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/108 ,  G11C11/401

CPC分类号： H01L27/10805 ,  G11C11/4097 ,  G11C7/18

摘要： A semiconductor memory device of the present invention comprises a plurality of word lines formed on a substrate, a plurality of bit lines perpendicular to the word lines and divided into bit-line groups in the column direction along the word line, each group containing three bit lines, and arrays of memory cells arranged at the intersections of word lines and bit lines, wherein two memory cells are placed at two of every three adjacent intersections arranged in each of the row and column directions, and where these memory cell arrays are divided into subarrays in the row direction, each of the cell arrays is divided into cell blocks in the row direction, two of the three bit lines in each bit-line group along the bit line are crossed each other between adjacent cell blocks, and a plurality of sense amplifiers are placed between adjacent cell arrays so as to correspond to cell blocks.

摘要翻译： 本发明的半导体存储器件包括形成在基板上的多条字线，与字线垂直的多个位线，沿着字线在列方向上分成位线组，每组包含三位 线和排列在字线和位线的交点处的存储器单元阵列，其中两个存储单元被放置在布置在行和列方向中的每一个中的每三个相邻交点中的两个处，并且其中这些存储单元阵列被分成 在行方向上的子阵列中，每个单元阵列被划分为行方向上的单元块，沿位线的每个位线组中的三个位线中的两个在相邻单元块之间彼此交叉，并且多个 感测放大器被放置在相邻单元阵列之间，以便对应于单元块。

公开(公告)号：US5396450A

公开(公告)日：1995-03-07

申请号：US123466

申请日：1993-09-20

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/10805

摘要： A dynamic random access memory device includes a semiconductor substrate, a plurality of parallel word lines on the substrate, and a plurality of pairs of bit lines transverse to the word lines on the substrate. An array of one-transistor memory cells are selectively arranged at the cross points as defined between the word lines and the bit lines. The array is subdivided into a plurality of subarray sections. A sense amplifier section is connected to the bit lines. The sense amplifier section includes first and second sense amplifier circuits. Adjacent bit-line pairs of the bit lines include a first bit-line pair and a second bit-line pair, one of which has a folded bit-line arrangement being included in a certain subarray section to be connected to the first sense amplifier circuit, and the other of which has an open bit-line arrangement that extends into the subarray section and another subarray section adjacent thereto, and is connected to the second sense amplifier circuit.

公开(公告)号：US4811290A

公开(公告)日：1989-03-07

申请号：US31615

申请日：1987-03-30

申请人： Shigeyoshi Watanabe

发明人： Shigeyoshi Watanabe

IPC分类号： H01L27/10 ,  G11C11/4091 ,  G11C11/4099 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24 ,  G11C7/00

CPC分类号： G11C11/4099 ,  G11C11/4091

摘要： A dynamic random access memory including a sense amplifier having MOSFETs, which constitute a flip-flop, and an activating MOSFET. A memory cell includes a switching MOSFET and a capacitor having a grooved structure. A dummy cell includes a switching MOSFET and capacitor having a planar structure. The activating MOSFET has its gate coupled to a gate bias generator, which comprises a reference capacitor group consisting of planar type capacitors having a nearly constant capacitance, irrespective of the influence of process parameters, and a monitoring capacitor group consisting of capacitors having the same grooved structure and the same capacitance as the memory cell capacitor. The reference capacitor group, and the monitoring capacitor group are pre-charged. When the sensing operation starts, the reference capacitor group and the monitoring capacitor group are short-circuited, so that a charge reallocation is executed between these groups. When a word line driver functions, the gate of the switching MOSFET of the memory cell is open, thus transferring data of the memory cell capacitor and dummy cell capacitor onto bit line BL and BL. The voltage of the node between the reference and monitoring capacitor groups, which are short-circuited, is applied to the gate of the activating MOSFET of the sense amplifier after a predetermined time delay.

摘要翻译： 动态随机存取存储器包括构成触发器的具有MOSFET的读出放大器和激活MOSFET。 存储单元包括开关MOSFET和具有沟槽结构的电容器。 虚设单元包括具有平面结构的开关MOSFET和电容器。 激活MOSFET的栅极耦合到栅极偏置发生器，其包括由具有几乎恒定电容的平面型电容器组成的参考电容器组，与工艺参数的影响无关，以及由具有相同沟槽的电容器组成的监测电容器组 结构和与存储单元电容器相同的电容。 参考电容器组和监控电容组预充电。 当感测操作开始时，参考电容器组和监视电容器组短路，从而在这些组之间执行电荷重新分配。 当字线驱动器工作时，存储单元的开关MOSFET的栅极断开，从而将存储单元电容器和虚设单元电容器的数据传输到位线和上升沿B和BL。 在预定的时间延迟之后，将被短路的基准电压和监视电容器组之间的节点的电压施加到读出放大器的激活MOSFET的栅极。

公开(公告)号：US4777625A

公开(公告)日：1988-10-11

申请号：US89518

申请日：1987-08-26

申请人： Koji Sakui ,  Shigeyoshi Watanabe

发明人： Koji Sakui ,  Shigeyoshi Watanabe

IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4097 ,  H05B41/24 ,  G11C11/40

CPC分类号： G11C11/4097 ,  G11C11/4091

摘要： There is disclosed a divided-bit line type dynamic random access memory having parallel main bit line pairs which are formed on a substrate and to each of which sub-bit line pairs are provided in parallel with each other. Parallel word lines insulatively cross the sub-bit line pairs. Memory cells are provided at the crossing points of the sub-bit line pairs and the word lines. Each memory cell has a capacitor for storing information and a voltage-controlled switching transistor such as a MOSFET. First sense amplifier circuits are connected to the sub-bit line pairs, while second sense amplifier circuits are connected to the main bit line pairs. In a restoring mode, a specific sub-bit line pair, to which a selected memory cell is connected, is electrically disconnected from the corresponding main bit one pair, and a first sense amplifier circuit connected thereto is activated to perform a restoring operation. At this time, the remaining sub-bit line pairs other than the specific sub-bit line pair are also connected to the corresponding main bit line pair, and the first sense amplifier circuits of the remaining sub-bit line pairs are rendered inoperative to save power consumption.

摘要翻译： 公开了一种分割位线型动态随机存取存储器，其具有形成在衬底上的并行主位线对，并且每个子位线对彼此并联设置。 并行字线绝对地穿过子位线对。 在子位线对和字线的交叉点提供存储单元。 每个存储单元具有用于存储信息的电容器和诸如MOSFET的压控开关晶体管。 第一读出放大器电路连接到子位线对，而第二读出放大器电路连接到主位线对。 在恢复模式中，连接所选择的存储单元的特定子位线对与相应的主位一对电断开，并且连接到其上的第一读出放大器电路被激活以执行恢复操作。 此时，除了特定子位线对以外的剩余子位线对也连接到相应的主位线对，并且使剩余的子位线对的第一读出放大器电路不可操作地保存 能量消耗。

公开(公告)号：US4531202A

公开(公告)日：1985-07-23

申请号：US344049

申请日：1982-01-29

申请人： Shigeyoshi Watanabe ,  Sumio Tanaka

发明人： Shigeyoshi Watanabe ,  Sumio Tanaka

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/08 ,  G11C11/40

CPC分类号： G11C16/08

摘要： A semiconductor nonvolatile read only memory device has a voltage applying circuit which sets all word lines at ground potential in a stand-by mode and sets only a selected word line at a high level in an active mode. The word lines are connected to the gates of semiconductor nonvolatile memory transistors. Each of the memory transistors has the source (or drain) grounded and the drain (or source) connected to output lines. In a stand-by mode, the voltage applying circuit keeps all the word lines at ground potential. In an active mode, the voltage applying circuit applies a high level voltage only to the selected word line. The memory transistor connected to the selected word line produces data of "0" or "1" to the output line.

摘要翻译： 半导体非易失性只读存储器件具有电压施加电路，其以待机模式将所有字线设置为接地电位，并且在活动模式中仅将所选择的字线设置为高电平。 字线连接到半导体非易失性存储晶体管的栅极。 每个存储晶体管的源极（或漏极）接地，漏极（或源极）连接到输出线。 在待机模式下，电压施加电路使所有字线保持接地电位。 在有源模式下，电压施加电路仅对所选择的字线施加高电平电压。 连接到所选字线的存储晶体管对输出线产生“0”或“1”的数据。

公开(公告)号：US20080023241A1

公开(公告)日：2008-01-31

申请号：US11882291

申请日：2007-07-31

申请人： Shigeyoshi Watanabe

发明人： Shigeyoshi Watanabe

IPC分类号： B60K31/02 ,  G06F7/00

CPC分类号： B60W10/06 ,  B60W10/11

摘要： In a cruise control system installed in a vehicle and electrically connected to a plurality of switches installed therein, a detecting unit detects that one of the plurality of switches is operated. A cruise control unit executes cruise control of the vehicle based on an instruction corresponding to the one of the plurality of switches upon detection of the one of the plurality of switches being operated. When the detecting unit detects that, during the first switch being operated, the second switch is operated, and when a combination of first and second instructions sent from the detected first and second switches is matched with at least one predetermined combination of instructions to be sent from the plurality of switches, a cruise control disabling unit disables the cruise control unit to execute cruise control of the vehicle based on the second instruction.

摘要翻译： 在安装在车辆中的电气连接到安装在其中的多个开关的巡航控制系统中，检测单元检测到多个开关中的一个开关被操作。 在检测到所述多个开关中的一个开关被操作时，巡航控制单元基于与所述多个开关中的一个开关相对应的指令来执行车辆的巡航控制。 当检测单元检测到在操作的第一开关期间操作第二开关，并且当从检测到的第一和第二开关发送的第一和第二指令的组合与要发送的指令的至少一个预定组合匹配时 巡航控制禁止单元从多个开关中，基于第二指令使巡航控制单元不执行车辆的巡航控制。

公开(公告)号：US5838038A

公开(公告)日：1998-11-17

申请号：US478620

申请日：1995-06-07

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

IPC分类号： G11C7/18 ,  H01L27/108

CPC分类号： G11C7/18 ,  G11C2211/4013

摘要： A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a source and a drain one of which is connected to the bit line, a plurality of trenches each arranged to another set of source an drain regions and arranged to deviate in the word line direction in the respective active regions, those of the trenches which are adjacent with a through word line disposed therebetween being arranged to deviate in the bit line direction so as to be set closer to each other, a plurality of storage electrodes respectively formed in the trenches with capacitor insulative films disposed therebetween, and connection electrodes arranged between the word lines and each connecting the other of the source and drain to the storage electrode.

摘要翻译： 半导体存储器件包括布置在半导体衬底上的有源区域，使得在字线方向上相邻的有源区域在位线方向偏离的有源区域分别形成在有源区域中并且各自具有源极和漏极 其中一个连接到位线，多个沟槽，每个沟槽被布置成另一组源极漏极区域，并且被布置成在相应的有源区域中的字线方向偏离，与通过字相邻的沟槽的那些沟槽 配置在它们之间的线被布置为在位线方向上偏离以使得彼此更靠近，分别形成在沟槽中的多个存储电极，其中设置有电容器绝缘膜，以及布置在字线和每个连接之间的连接电极 另一个源极和漏极到存储电极。

公开(公告)号：US5508957A

公开(公告)日：1996-04-16

申请号：US312072

申请日：1994-09-26

申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

公开(公告)号：US5397723A

公开(公告)日：1995-03-14

申请号：US728585

申请日：1991-07-11

申请人： Riichiro Shirota ,  Masaki Momodomi ,  Ryozo Nakayama ,  Seiichi Aritome ,  Ryouhei Kirisawa ,  Tetsuro Endoh ,  Shigeyoshi Watanabe

发明人： Riichiro Shirota ,  Masaki Momodomi ,  Ryozo Nakayama ,  Seiichi Aritome ,  Ryouhei Kirisawa ,  Tetsuro Endoh ,  Shigeyoshi Watanabe

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265 ,  H01L21/465

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11517

摘要： A process for forming an array of FATMOS transistors serving as memory cells of a NAND cell type EEPROM. A multi-layered structure is provided on a substrate with two stacked conductive layers insulated by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from the substrate, the second or outer conductive layer being covered with a second insulative layer. The second insulative layer is etched to define a first array of etched layer portions. A photoresist layer is deposited and etched to define a second array of layer portions, each of which is positioned between two neighboring ones of the first array of layer portions. The multi-layered structure is etched with the first and second layer portions being as a mask, to thereby form an array of a plurality of pairs of insulated gate electrodes above the substrate. A chosen impurity is doped into the substrate with the insulated gate electrodes serving as a mask to thereby form impurity-doped regions in the substrate.

摘要翻译： 用于形成用作NAND单元型EEPROM的存储单元的FATMOS晶体管阵列的工艺。 多层结构设置在具有由中间绝缘层绝缘的两个层叠导电层的基板上，第一或内部导电层由与基板隔开的第一绝缘层，第二或外部导电层被第二 绝缘层。 蚀刻第二绝缘层以限定蚀刻层部分的第一阵列。 沉积和蚀刻光致抗蚀剂层以限定层部分的第二阵列，每个层部分位于层部分的第一阵列中的两个相邻的层部分之间。 用第一和第二层部分作为掩模蚀刻多层结构，从而在衬底上形成多对绝缘栅电极的阵列。 将所选择的杂质掺杂到衬底中，其中绝缘栅电极用作掩模，从而在衬底中形成杂质掺杂区域。

公开(公告)号：US5088060A

公开(公告)日：1992-02-11

申请号：US634325

申请日：1990-12-26

申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Masaki Momodomi ,  Tomoharu Tanaka ,  Fujio Masuoka ,  Shigeyoshi Watanabe

发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Masaki Momodomi ,  Tomoharu Tanaka ,  Fujio Masuoka ,  Shigeyoshi Watanabe

IPC分类号： G11C16/04

CPC分类号： G11C16/0483

摘要： An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.

摘要翻译： 具有NAND单元结构的电可擦除可编程只读存储器具有并行位线，以及限定NAND单元块的存储器单元，每个存储单元具有存储单元晶体管的串联电路。 每个晶体管都有一个浮动栅极和一个控制栅极。 并行字线连接到单元晶体管的控制栅极。 在数据写入模式下使用第一，第二和第三中间电压：第一电压低于“H”电平电压并高于“L”电平电压; 第二和第三电压高于第一电压并低于“H”电平电压。 将数据写入NAND单元块的选定的存储单元晶体管中，通过将“H”电平电压施加到连接到所选晶体管的字线，将第二电压施加到剩余的未选字线，施加相应的位线 其中所选择的晶体管具有根据数据的逻辑电平选择的第一和第三电压中的一个，以及施加具有第三电压的未选择的位线，由此通过隧道从所选择的浮动栅极或者所选择的浮动栅极 存储单元晶体管。