公开(公告)号：US07439153B2

公开(公告)日：2008-10-21

申请号：US11541656

申请日：2006-10-03

申请人： Nobuo Tsuboi ,  Motoshige Igarashi

发明人： Nobuo Tsuboi ,  Motoshige Igarashi

IPC分类号： H01L21/00

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

摘要翻译： 采用一种结构来提供在栅极2a和栅极2b之间提供局部布线3a的SRAM单元的布局，并连接有源区域1a和有源区域1b。 这消除了在栅极2a和栅极2b之间提供接触的必要性。 因此，可以在短边方向上减小存储单元区域C的尺寸。 此外，采用栅极2c的左端从栅极2a退出的结构和连接沿对角线方向设置的有源区域b和栅极2c的局部布线3b。 这允许栅极2a向存储单元区域C的中心移动。

公开(公告)号：US20070080423A1

公开(公告)日：2007-04-12

申请号：US11541656

申请日：2006-10-03

申请人： Nobuo Tsuboi ,  Motoshige Igarashi

发明人： Nobuo Tsuboi ,  Motoshige Igarashi

IPC分类号： H01L21/76

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

摘要翻译： 采用一种结构来提供在栅极2a和栅极2b之间提供局部布线3a的SRAM单元的布局，并连接有源区域1a和有源区域1b。 这消除了在栅极2a和栅极2b之间提供接触的必要性。 因此，可以在短边方向上减小存储单元区域C的尺寸。 此外，采用栅极2c的左端从栅极2a退出的结构和连接沿对角线方向设置的有源区域b和栅极2c的局部布线3b。 这允许栅极2a向存储单元区域C的中心移动。

公开(公告)号：US06693820B2

公开(公告)日：2004-02-17

申请号：US10061276

申请日：2002-02-04

申请人： Koji Nii ,  Motoshige Igarashi

发明人： Koji Nii ,  Motoshige Igarashi

IPC分类号： G11C1100

CPC分类号： G11C11/412 ,  Y10S257/903 ,  Y10S257/904

摘要： The semiconductor memory device includes two PMOS transistors that make the SRAM memory cell. The gate insulating films of these PMOS transistors are formed using a material that has a high permittivity. As a result, the capacitance of memory nodes is increased, and the probability of soft errors is lowered.

公开(公告)号：US06593214B1

公开(公告)日：2003-07-15

申请号：US10206209

申请日：2002-07-29

申请人： Motoshige Igarashi

发明人： Motoshige Igarashi

IPC分类号： H01L2120

CPC分类号： H01L21/823828 ,  H01L21/266 ,  H01L21/28512 ,  H01L21/76802 ,  H01L21/82385 ,  H01L27/0207

摘要： A photoresist is provided with an opening as a dummy pattern in a space area, i.e., a dummy region, other than a pattern of elements and circuits in one chip, thereby increasing the number of openings in the photoresist and performing ion implantation. This reduces the number of ions entering into the photoresist. As a result, the area in which the photoresist hardens due to the entering ions can be reduced, resulting in improved removability of the photoresist. The occurrence of charge-up can also be reduced. With a reduction in the area of regions other than the openings in the photoresist, a location where strong surface tension is generated can hardly be present. This allows the dimensional accuracy of the photoresist to be improved without making the photoresist thin in film thickness.

摘要翻译： 光致抗蚀剂在一个芯片中的元件和电路图案之外的空间区域，即虚拟区域中设置有作为虚设图案的开口，从而增加光致抗蚀剂中的开口数量并进行离子注入。 这减少了进入光致抗蚀剂的离子的数量。 结果，可以减少由于进入的离子而使光致抗蚀剂硬化的区域，从而提高了光致抗蚀剂的可除去性。 也可以减少充电的发生。 除了光致抗蚀剂中的开口以外的区域的减少，难以产生强表面张力的位置。 这使得可以改善光致抗蚀剂的尺寸精度，而不会使光致抗蚀剂的膜厚度变薄。

公开(公告)号：US20120187504A1

公开(公告)日：2012-07-26

申请号：US13354077

申请日：2012-01-19

申请人： Motoshige Igarashi ,  Yuki Igarashi

发明人： Motoshige Igarashi ,  Yuki Igarashi

IPC分类号： H01L27/105 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L27/1104 ,  H01L21/76895 ,  H01L27/0207

摘要： A semiconductor device has a high-speed circuit and a high-density circuit, each having at least two field effect transistors and two gate electrodes. In the high-speed circuit, a first gate electrode of a first field effect transistor and a second gate electrode of a second field effect transistor are separated by a first pitch. In the high-density circuit, a third gate electrode of a third field effect transistor and a fourth gate electrode of a fourth field effect transistor are separated by a second pitch. The first pitch is larger than the second pitch. Provision of a notch in the third gate electrode of the third field effect transistor in the high-density circuit, at a portion reached by a shared contact hole shared by the third gate electrode and the fourth transistor, increases the contact area between the shared contact hole and an impurity region source/drain of the fourth transistor.

摘要翻译： 半导体器件具有高速电路和高密度电路，每个具有至少两个场效应晶体管和两个栅电极。 在高速电路中，第一场效应晶体管的第一栅电极和第二场效应晶体管的第二栅电极以第一间距分开。 在高密度电路中，第三场效应晶体管的第三栅电极和第四场效应晶体管的第四栅电极以第二间距分开。 第一节距大于第二节距。 在高密度电路中的第三场效应晶体管的第三栅电极中，在由第三栅极电极和第四晶体管共享的共用接触孔所达到的部分处设置一个凹口，增加共享触点之间的接触面积 空穴和第四晶体管的杂质区源极/漏极。

公开(公告)号：US20110024847A1

公开(公告)日：2011-02-03

申请号：US12901858

申请日：2010-10-11

申请人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L27/092

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US07821076B2

公开(公告)日：2010-10-26

申请号：US12422278

申请日：2009-04-12

申请人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US20080116526A1

公开(公告)日：2008-05-22

申请号：US12007496

申请日：2008-01-11

申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

IPC分类号： H01L27/06

CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

公开(公告)号：US06818932B2

公开(公告)日：2004-11-16

申请号：US10003404

申请日：2001-12-06

申请人： Koji Nii ,  Motoshige Igarashi

发明人： Koji Nii ,  Motoshige Igarashi

IPC分类号： H01L2976

CPC分类号： G11C11/4125 ,  H01L21/76895 ,  H01L27/1104

摘要： There is provided a semiconductor device including a transistor formed by means of a common contact hole that connects a gate electrode, and a diffused layer forming a source/drain terminal; and a semiconductor device comprising the gate electrode of the transistor, and a connecting terminal to which capacitance between substrates and capacitance between the gate electrode and the source/drain terminal are added, thereby improving the soft error resistance caused by alpha rays and neutron beams.

摘要翻译： 提供了一种半导体器件，其包括通过连接栅电极的公共接触孔和形成源极/漏极端子的扩散层形成的晶体管; 以及包括晶体管的栅电极的半导体器件，以及连接端子，基板之间的电容与栅极电极和源极/漏极端子之间的电容相加，从而提高由α射线和中子束引起的软误差电阻。

公开(公告)号：US06753246B2

公开(公告)日：2004-06-22

申请号：US10419770

申请日：2003-04-22

申请人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

发明人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

IPC分类号： H01L214763

CPC分类号： H01L21/31053 ,  H01L21/76229

摘要： The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.

摘要翻译： 半导体器件包括半导体衬底，并且在半导体衬底中的元件隔离区域中具有间距小于第一A / A虚设图形的间距的第一有源区A / A虚拟图案和第二A / A虚拟图案 。 第一A / A虚拟图案的放置和第二A / A虚拟图案的放置在单独的步骤中进行。 半导体衬底可以被划分成多个网格区域，并且可以根据网格区域被位于其中的元素图案占据的区域而将虚设图案放置在每个网格区域中。