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    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110024847A1

    公开(公告)日：2011-02-03

    申请号：US12901858

    申请日：2010-10-11

    申请人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

    发明人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

    摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

    摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

    Method of manufacturing semiconductor device, and semiconductor device
    6.
    发明授权
    Method of manufacturing semiconductor device, and semiconductor device 有权
    制造半导体器件的方法和半导体器件

    公开(公告)号：US08269284B2

    公开(公告)日：2012-09-18

    申请号：US13019600

    申请日：2011-02-02

    申请人： Koji Nil ,  Motoshige Igarashi

    发明人： Koji Nil ,  Motoshige Igarashi

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L21/823412 ,  H01L27/11 ,  H01L27/1104

    摘要： There are provided a method of manufacturing a semiconductor device which achieves a reduction in implantation masks, and such a semiconductor device. By implanting boron into NMOS regions using a resist mask and another resist mask as the implantation masks, p-type impurity regions serving as the halo regions of access transistors and drive transistors are formed. By further implanting phosphorus or arsenic into a PMOS region using another resist mask as the implantation mask, n-type impurity regions serving as the halo regions of load transistors are formed.

    摘要翻译： 提供了一种制造半导体器件的方法，其实现了注入掩模的减少以及这种半导体器件。 通过使用抗蚀剂掩模和另一抗蚀剂掩模将硼注入NMOS区域作为注入掩模，形成用作存取晶体管和驱动晶体管的晕区的p型杂质区。 通过使用另一抗蚀剂掩模作为注入掩模将磷或砷进一步注入PMOS区，形成用作负载晶体管的晕区的n型杂质区。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
    7.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法和半导体器件

    公开(公告)号：US20110193173A1

    公开(公告)日：2011-08-11

    申请号：US13019600

    申请日：2011-02-02

    申请人： Koji NII ,  Motoshige Igarashi

    发明人： Koji NII ,  Motoshige Igarashi

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L21/823412 ,  H01L27/11 ,  H01L27/1104

    摘要： There are provided a method of manufacturing a semiconductor device which achieves a reduction in implantation masks, and such a semiconductor device. By implanting boron into NMOS regions using a resist mask and another resist mask as the implantation masks, p-type impurity regions serving as the halo regions of access transistors and drive transistors are formed. By further implanting phosphorus or arsenic into a PMOS region using another resist mask as the implantation mask, n-type impurity regions serving as the halo regions of load transistors are formed.

    摘要翻译： 提供了一种制造半导体器件的方法，其实现了注入掩模的减少以及这种半导体器件。 通过使用抗蚀剂掩模和另一抗蚀剂掩模将硼注入NMOS区域作为注入掩模，形成用作存取晶体管和驱动晶体管的晕区的p型杂质区。 通过使用另一抗蚀剂掩模作为注入掩模将磷或砷进一步注入PMOS区，形成用作负载晶体管的晕区的n型杂质区。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF FOR REDUCING THE AREA OF THE MEMORY CELL REGION
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF FOR REDUCING THE AREA OF THE MEMORY CELL REGION 失效
    用于减少存储单元区域的半导体器件及其制造方法

    公开(公告)号：US20100093145A1

    公开(公告)日：2010-04-15

    申请号：US12636408

    申请日：2009-12-11

    申请人： Nobuo TSUBOI ,  Motoshige Igarashi

    发明人： Nobuo TSUBOI ,  Motoshige Igarashi

    IPC分类号： H01L21/8239

    CPC分类号： H01L27/1104 ,  H01L27/11

    摘要： A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

    摘要翻译： 采用在栅极2a和栅极2b之间提供局部布线3a并连接有源区域1a和有源区域1b的SRAM单元布局的结构。 这消除了在栅极2a和栅极2b之间提供接触的必要性。 因此，可以在短边方向上减小存储单元区域C的尺寸。 此外，采用栅极2c的左端从栅极2a退出的结构和连接沿对角线方向设置的有源区域1b和栅极2c的局部布线3b。 这允许栅极2a朝向存储单元区域C的中心移动。

    Semiconductor device having structures that can avoid deterioration caused by the manufacturing processing
    9.
    发明授权
    Semiconductor device having structures that can avoid deterioration caused by the manufacturing processing 失效
    具有能够避免由制造加工引起的劣化的结构的半导体装置

    公开(公告)号：US06683351B2

    公开(公告)日：2004-01-27

    申请号：US10225128

    申请日：2002-08-22

    申请人： Kiyoaki Morita ,  Motoshige Igarashi

    发明人： Kiyoaki Morita ,  Motoshige Igarashi

    IPC分类号： H01L2362

    CPC分类号： H01L27/0629 ,  H01L23/485 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device restricting the antenna effect without complicating the manufacturing process and a manufacturing method of such a semiconductor device are provided. In addition, a semiconductor device ensuring matching or equality in characteristics of pairing transistors and a manufacturing method of such a semiconductor device are provided. The semiconductor device includes an interconnection that is placed on an insulating film covering a gate electrode and a semiconductor substrate and is electrically connected to the gate electrode. The semiconductor device also includes a dummy transistor that is formed on the semiconductor substrate and is unprovided with an interconnection required for a transistor. The interconnection is electrically connected to a source/drain region of the dummy transistor.

    摘要翻译： 提供限制天线效应而不使制造工艺复杂化的半导体器件和这种半导体器件的制造方法。 此外，提供确保配对晶体管的特性匹配或相等的半导体器件以及这种半导体器件的制造方法。 半导体器件包括布置在覆盖栅电极和半导体衬底的绝缘膜上并且与栅电极电连接的互连。 半导体器件还包括形成在半导体衬底上的虚拟晶体管，并且未提供晶体管所需的互连。 互连电连接到虚拟晶体管的源/漏区。