公开(公告)号：US5805789A

公开(公告)日：1998-09-08

申请号：US846746

申请日：1997-04-03

申请人： William Vincent Huott ,  Tin-Chee Lo ,  Pradip Patel ,  Timothy John Slegel

发明人： William Vincent Huott ,  Tin-Chee Lo ,  Pradip Patel ,  Timothy John Slegel

IPC分类号： G06F11/22 ,  G06F11/27 ,  G06F11/273 ,  G11C29/00 ,  G11C29/32 ,  G11C29/44 ,  G06F11/00

CPC分类号： G11C29/789 ,  G06F11/2294 ,  G11C29/16 ,  G11C29/44 ,  G06F11/22 ,  G06F11/2205 ,  G06F11/27 ,  G11C2029/0407 ,  G11C29/32

摘要： Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test) system having mirror image fuse registers enabling scan of failed addresses to be used to replace hardware errors detected during power-on at a customer location. The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy and useful for enabling array self-tests to be performed in a customer's office at power-on reset.

摘要翻译： 计算机系统元件具有冗余区域的VLSI阵列和具有镜像熔丝寄存器的ABIST（阵列内置自检）系统，其能够扫描失败的地址，以替代在客户位置上电时检测到的硬件错误。 ABIST控制器允许修改测试功能（例如测试模式，读/写访问和测试序列），而不会对测试逻辑进行硬件更改。 测试顺序由逻辑测试向量控制，可以改变，使开发复杂测试序列的任务相对容易和有用，可以在上电复位时在客户办公室中进行阵列自检。

公开(公告)号：US06933602B1

公开(公告)日：2005-08-23

申请号：US10620074

申请日：2003-07-14

申请人： Pradip Patel ,  Maurice Othieno ,  Manickam Thavarajah ,  Severino A. Legaspi, Jr.

发明人： Pradip Patel ,  Maurice Othieno ,  Manickam Thavarajah ,  Severino A. Legaspi, Jr.

IPC分类号： H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/48 ,  H05K7/20

CPC分类号： H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate includes at least one electrical ground plane and includes a plurality solder balls formed on a surface thereof. The solder balls include a set of “thermal” solder balls that are positioned near the perimeter of the package and electrically connected with a ground plane of the package. The IC die is electrically connected with the ground plane that is connected with the “thermal” solder balls. A heat spreader is mounted on the package with conductive mounting pegs that are electrically connected with the ground plane. The heat spreader is in thermal communication with the die and also in thermal communication with the set of “thermal” solder balls. This configuration enables a portion of the heat generated by the die to be dissipated from the die through the heat spreader into the set of “thermal” solder balls. Additionally, the package can be configured so that the combination of the electrically connected heat spreader, ground plane, and conductive mounting pegs operate together as a electromagnetic shield that reduces the amount of electrical noise of the package.

摘要翻译： 本发明的实施例包括半导体集成电路封装，其包括具有附接到其上的集成电路管芯的衬底。 基板包括至少一个电接地平面，并且包括在其表面上形成的多个焊球。 焊球包括一组“热”焊球，其位于封装周边附近并与封装的接地平面电连接。 IC芯片与与“热”焊球连接的接地平面电连接。 散热器安装在封装上，导电安装钉与地平面电连接。 散热器与模具热连通，并且还与一组“热”焊球热连通。 这种配置使得由模具产生的热量的一部分能够通过散热器从模具中消散到一组“热”焊球中。 此外，封装可以被配置成使得电连接的散热器，接地平面和导电安装钉的组合作为电磁屏蔽一起工作，这减少了封装的电噪声量。

公开(公告)号：US5397997A

公开(公告)日：1995-03-14

申请号：US57590

申请日：1993-05-06

申请人： David Tuckerman ,  Pradip Patel

发明人： David Tuckerman ,  Pradip Patel

IPC分类号： G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  G01R31/02

CPC分类号： G01R31/2863 ,  H01L2224/0401 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14

摘要： A device and method for burn-in of bare chips prior to assembly into a multichip module. Each die to be tested is positioned with its I/O pads positioned to face an interconnection burn-in test substrate which may be a silicon circuit board. Each die is temporarily electrically connected to the substrate by a deformable solder bump.

摘要翻译： 在组装到多芯片模块之前，裸芯片的老化装置和方法。 要测试的每个管芯的定位是将I / O焊盘定位成面对可能是硅电路板的互连老化测试基板。 每个管芯通过可变形的焊料凸块临时电连接到衬底。

公开(公告)号：US20060156130A1

公开(公告)日：2006-07-13

申请号：US11008371

申请日：2004-12-09

申请人： William Huott ,  David Lund ,  Kenneth Marz ,  Bryan Mechtly ,  Pradip Patel

发明人： William Huott ,  David Lund ,  Kenneth Marz ,  Bryan Mechtly ,  Pradip Patel

IPC分类号： G01R31/28

CPC分类号： G06F12/0802 ,  G06F12/126 ,  G11C29/44 ,  G11C29/88 ,  G11C2029/0401 ,  G11C2029/0407 ,  G11C2029/4402

摘要： A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.

摘要翻译： 提供了一种包括具有高速缓存存储器的处理器的计算系统。 高速缓冲存储器包括多个可独立配置的子部分，每个细分包括存储器阵列。 计算系统的服务元素（SE）可操作以执行内置自检（BIST）以测试高速缓冲存储器，BIST可操作以确定任何子细分是否有缺陷。 当确定由BIST确定为有缺陷的高速缓冲存储器的一个细分是不可修复时，SE从系统配置逻辑地删除缺陷细分，并且SE可操作以允许处理器在没有逻辑删除的情况下操作 细分。 当有多个缺陷细分超过阈值时，SE还可操作以确定处理器有缺陷。

公开(公告)号：US20060203578A1

公开(公告)日：2006-09-14

申请号：US11079816

申请日：2005-03-14

申请人： Patrick Meaney ,  William Huott ,  Thomas Knips ,  David Lund ,  Bryan Mechtly ,  Pradip Patel

发明人： Patrick Meaney ,  William Huott ,  Thomas Knips ,  David Lund ,  Bryan Mechtly ,  Pradip Patel

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C11/41 ,  G11C15/00 ,  G11C29/4401 ,  G11C29/789 ,  G11C2029/0407 ,  G11C2029/1208

摘要： An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call home if spare fuses are not available, schedule soft fuse repairs for the next system restart, schedule line deletes at the next restart, store delete and fuse repairs in a table (tagged with electronic serial id, timestamp of delete or ABIST fail event, address, and type of failure) and proactively call home if there were any missed deletes that were not logged. Fuse information can also be more permanently stored into hardware electronic fuses and/or EPROMs. During a restart, previous repairs are able to be applied to the machine so that ABIST will run successfully and previous deletes to be maintained with checking to allow some ABIST failures which are protected by the line deletes to pass.

摘要翻译： 一种用于保护计算机系统免受阵列可靠性故障的装置和方法使用阵列内置自检逻辑以及代码和硬件来删除有缺陷的高速缓存行或集合，识别相应的保险丝修复值，如果备用保险丝为主动式，则主动呼叫家庭 不可用，为下一次重新启动计划软保险丝修复，下次重新启动时计划行删除，在表中存储删除和保险丝修复（标记为电子序列号，删除时间戳或ABIST失败事件，地址和故障类型 ），并且如果有任何未被记录的遗漏的删除事件，则主动呼叫回家。 保险丝信息也可以更加永久地存储在硬件电子保险丝和/或EPROM中。 在重新启动期间，以前的修复可以应用于机器，以便ABIST将成功运行，以前的删除将通过检查进行维护，以允许由删除行保护的一些ABIST故障通过。

公开(公告)号：US07436060B2

公开(公告)日：2008-10-14

申请号：US10865179

申请日：2004-06-09

申请人： Pradip Patel ,  Maurice O. Othieno ,  Manickam Thavarajah ,  Severino A. Legaspi, Jr.

发明人： Pradip Patel ,  Maurice O. Othieno ,  Manickam Thavarajah ,  Severino A. Legaspi, Jr.

IPC分类号： H01L23/36

CPC分类号： H01L23/3675 ,  H01L23/10 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor integrated circuit package incorporating a preformed one-piece mold cap and heatspreader assembly is disclosed. One implementation includes a substrate with a die attached to the substrate. The die is electrically connected with electrical connections formed on the substrate using bonding wires. A preformed one-piece integrated mold cap and heatspreader assembly attached to the substrate to enclose at least a portion of the bonding wires and the die. Methods of assembling semiconductor integrated circuit packages using a preformed one-piece integrated mold cap and heatspreader assembly are also disclosed.

摘要翻译： 公开了一种结合有预制的一体式模具盖和散热器组件的半导体集成电路封装。 一个实施方案包括具有附接到基底的管芯的基底。 模具使用接合线与形成在基板上的电连接电连接。 附着在基板上的预成型的整体式模具盖和散热器组件，以封闭至少一部分接合线和模具。 还公开了使用预成型的一体式模制帽和散热器组件组装半导体集成电路封装的方法。

公开(公告)号：US20060036062A1

公开(公告)日：2006-02-16

申请号：US11132991

申请日：2005-05-19

申请人： Sonti Ramakrishna ,  Vidhya Rangaswamy ,  Dharmendra Jain ,  Raj Jagdambalal ,  Pradip Patel ,  Debojyoti Kar ,  Subramania Ramachandran ,  Pralhad Ganeshpure ,  Uma Satpathy

发明人： Sonti Ramakrishna ,  Vidhya Rangaswamy ,  Dharmendra Jain ,  Raj Jagdambalal ,  Pradip Patel ,  Debojyoti Kar ,  Subramania Ramachandran ,  Pralhad Ganeshpure ,  Uma Satpathy

IPC分类号： C08G63/08

CPC分类号： C12P7/44 ,  C12P7/56

摘要： The present invention relates to an efficient process for producing polylactic acid from fermentation of renewable agricultural feed-stocks not limited to molasses or cane bagasse employed as starting material. The present invention in particular provides a cost effective and industrially scalable process for producing polylactic acid obtained by fermentation of Lactic acid having industrial applications.

公开(公告)号：US5659551A

公开(公告)日：1997-08-19

申请号：US572843

申请日：1995-12-14

申请人： William Vincent Huott ,  Tin-Chee Lo ,  Pradip Patel ,  Timothy John Slegel

发明人： William Vincent Huott ,  Tin-Chee Lo ,  Pradip Patel ,  Timothy John Slegel

IPC分类号： G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G11C29/00 ,  G11C29/10 ,  G11C29/16 ,  G11C29/32 ,  G06F11/00

CPC分类号： G06F11/22 ,  G01R31/318385 ,  G06F11/2236 ,  G06F11/2294 ,  G11C29/16 ,  G11C29/789 ,  G11C29/10 ,  G11C29/32

摘要： Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test) system having mirror image fuse registers enabling scan of failed addresses to be used to replace hardware errors detected during power-on at a customer location. The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy and useful for enabling array self-tests to be performed in a customer's office at power-on reset.

摘要翻译： 计算机系统元件具有冗余区域的VLSI阵列和具有镜像熔丝寄存器的ABIST（阵列内置自检）系统，其能够扫描失败的地址，以替代在客户位置上电时检测到的硬件错误。 ABIST控制器允许修改测试功能（例如测试模式，读/写访问和测试序列），而不会对测试逻辑进行硬件更改。 测试顺序由逻辑测试向量控制，可以改变，使开发复杂测试序列的任务相对容易和有用，可以在上电复位时在客户办公室中进行阵列自检。