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公开(公告)号：US20210280635A1
公开(公告)日：2021-09-09
申请号：US17189107
申请日：2021-03-01
Applicant: Kioxia Corporation
Inventor： Hiroki TOKUHIRA , Tsuyoshi KONDO , Mutsumi OKAJIMA , Yoshihiro UEDA
Abstract: A magnetic memory of an embodiment includes: a first magnetic member including a first and second portions and extending in a first direction; a first and second wirings disposed to be apart from the first magnetic member and extending in a second direction intersecting the first direction, the first and the second wirings being separated from each other in a third direction intersecting the first and second directions, the first magnetic member being disposed to be apart from a region between the first wiring and the second wiring in the first direction; and a second magnetic member surrounding at least parts of the first and second wirings, the second magnetic member including a third portion located to be more distant from the first magnetic member, a fourth portion located to be closer to the first magnetic member, and a fifth portion located in the region.
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公开(公告)号：US20240324174A1
公开(公告)日：2024-09-26
申请号：US18605986
申请日：2024-03-15
Applicant: Kioxia Corporation
Inventor： Takafumi MASUDA , Mutsumi OKAJIMA , Nobuyoshi SAITO , Keiji IKEDA
IPC: H10B12/00
Abstract: A semiconductor memory device includes memory layers arranged in a first direction and a via-wiring extending in the first direction. The plurality of memory layers each include a semiconductor layer electrically connected to the via-wiring, a gate electrode opposed to surfaces of the semiconductor layer in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, a wiring disposed on the other side in the second direction with respect to the semiconductor layer, and a connection wiring connected to the gate electrode and the wiring. The connection wiring includes a first part extending in the second direction along a side surface of the gate electrode in the third direction and a second part continuous with the first part, extending in the third direction along a side surface of the wiring in the second direction.
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公开(公告)号：US20240312911A1
公开(公告)日：2024-09-19
申请号：US18601745
申请日：2024-03-11
Applicant: Kioxia Corporation
Inventor： Takafumi MASUDA , Mutsumi OKAJIMA , Nobuyoshi SAITO , Keiji IKEDA
IPC: H01L23/528 , H01L23/522 , H10B12/00
CPC classification number: H01L23/5283 , H01L23/5226 , H01L23/528 , H10B12/315 , H10B12/482
Abstract: A semiconductor memory device includes a memory layer and a via-wiring extending in a first direction. The memory layer includes a semiconductor layer electrically connected to the via-wiring, a gate electrode including parts opposed to surfaces of the semiconductor layer on one side and the other side in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, and a wiring disposed on the other side in the second direction with respect to the semiconductor layer. In a cross-sectional surface perpendicular to the first direction and including one of the parts of the gate electrode, the via-wiring includes a surface opposed to the gate electrode and a surface not opposed to the gate electrode. A part of the gate electrode is disposed on a memory portion side with respect to the via-wiring in the second direction.
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公开(公告)号：US20240090203A1
公开(公告)日：2024-03-14
申请号：US18455732
申请日：2023-08-25
Applicant: Kioxia Corporation
Inventor： Takanori AKITA , Kotaro NODA , Seiichi URAKAWA , Mutsumi OKAJIMA
IPC: H10B12/00
CPC classification number: H10B12/482 , H10B12/02 , H10B12/33
Abstract: A semiconductor storage device includes a first oxide semiconductor layer that extends in a first direction; a second oxide semiconductor layer that extends in the first direction and is adjacent to the first oxide semiconductor layer in a second direction intersecting to the first direction; first wiring that extends in a third direction intersecting to the first direction and overlaps with the first oxide semiconductor layer in the third direction; second wiring that extends in the third direction and overlaps with the second oxide semiconductor layer in the third direction; a first insulating film that is provided between the first wiring and the first oxide semiconductor layer; a second insulating film that is provided between the second wiring and the second oxide semiconductor layer; a first conductor that is provided on the first oxide semiconductor layer; a second conductor that is provided on the second oxide semiconductor layer; and an insulating layer that has a gap between the first conductor and the second conductor or between the first wiring and the second wiring.
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Patent Agency Ranking
公开(公告)号：US20240087616A1
公开(公告)日：2024-03-14
申请号：US18463686
申请日：2023-09-08
Applicant: Kioxia Corporation
Inventor： Takafumi MASUDA , Nobuyoshi SAITO , Mutsumi OKAJIMA , Keiji IKEDA
Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first and a second via wirings having different positions in a second direction. The memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring; and an electrode provided in a current path between the second transistor and the wiring. The second transistor comprises: a semiconductor layer electrically connected to the electrode and the second via wiring; and a gate electrode facing the semiconductor layer. The semiconductor layer faces at least one of surfaces on one side or the other side in the first direction of the gate electrode. The electrode includes a portion arranged with the second via wiring in a third direction.
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公开(公告)号：US20240038280A1
公开(公告)日：2024-02-01
申请号：US18184792
申请日：2023-03-16
Applicant: Kioxia Corporation
Inventor： Takafumi MASUDA , Mutsumi OKAJIMA , Nobuyoshi SAITO , Keiji IKEDA
IPC: G11C5/10 , G11C11/4097 , G11C11/4096
CPC classification number: G11C5/10 , G11C11/4097 , G11C11/4096
Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first wiring extending in the first direction. The memory layers each comprise: a memory portion; a transistor; and a second wiring. The transistor comprises: a semiconductor layer electrically connected between the memory portion and the first wiring; a gate electrode facing the semiconductor layer and electrically connected to the second wiring; and a gate insulating film provided between the semiconductor layer and the gate electrode. The semiconductor layer faces surfaces of the gate electrode on one side and the other side in the first direction. In a cross section perpendicular to the first direction and including a part of the transistor corresponding to one of the memory layers, the first wiring comprises: a first surface in contact with the transistor; and a second surface not in contact with the transistor.
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27.发明公开公开(公告)号：US20230197857A1
公开(公告)日：2023-06-22
申请号：US17842457
申请日：2022-06-16
Applicant: Kioxia Corporation
Inventor： Taro SHIOKAWA , Kiwamu SAKUMA , Keiko SAKUMA , Mutsumi OKAJIMA , Kazuhiro MATSUO , Masaya TODA
IPC: H01L29/786 , H01L27/108 , H01L29/66
CPC classification number: H01L29/78642 , H01L27/1082 , H01L29/7869 , H01L29/66969 , H01L27/10873
Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer between the first electrode and the second electrode and including a first region surrounded by the first electrode in a plane perpendicular to a first direction from the first electrode toward the second electrode; a gate electrode facing the oxide semiconductor layer; a gate insulating layer; a first insulating layer between the gate electrode and the first electrode; and a second insulating layer between the gate electrode and the second electrode. A first maximum distance between a first portion of the first electrode and a second portion of the first electrode in a second direction in a cross section parallel to the first direction is larger than a minimum distance between a third portion of the first insulating layer and a fourth portion of the first insulating layer in the second direction.
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公开(公告)号：US20220310581A1
公开(公告)日：2022-09-29
申请号：US17839431
申请日：2022-06-13
Applicant: Kioxia Corporation
Inventor： Mutsumi OKAJIMA
Abstract: According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.
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公开(公告)号：US20210305230A1
公开(公告)日：2021-09-30
申请号：US17017101
申请日：2020-09-10
Applicant: KIOXIA CORPORATION
Inventor： Mutsumi OKAJIMA
Abstract: According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.
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