公开(公告)号：US07516426B2

公开(公告)日：2009-04-07

申请号：US11561537

申请日：2006-11-20

申请人： Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

发明人： Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

IPC分类号： G06F17/50

CPC分类号： H01L27/088 ,  H01L21/823437 ,  H01L27/0207

摘要： Methods of improving operational parameters between at least a pair of matched transistors, and a set of transistors, are disclosed. One embodiment of a method includes a method of improving at least one of a threshold voltage (Vt) mismatch and current drive between at least a pair of matched transistors for analog applications, the method comprising: forming at least a pair of transistors, each with a gate having a plurality of connected fingers; and optimizing a total length of a channel under the plurality of fingers to attain at least one of: a) a reduced threshold voltage mismatch between the at least pair of transistors, and b) increased current drive for a given threshold voltage mismatch, between the at least pair of transistors, each finger having a length less than an overall length of the channel.

摘要翻译： 公开了改善至少一对匹配晶体管之间的操作参数的方法和一组晶体管。 方法的一个实施例包括一种改进用于模拟应用的至少一对匹配晶体管之间的阈值电压（Vt）失配和电流驱动中的至少一个的方法，所述方法包括：形成至少一对晶体管，每个晶体管具有 具有多个连接的手指的门; 以及优化所述多个指状物下的通道的总长度以达到以下至少一个：a）所述至少一对晶体管之间的阈值电压失配降低，以及b）对于给定阈值电压失配的增加的电流驱动， 至少一对晶体管，每个手指的长度小于通道的总长度。

公开(公告)号：US07302376B2

公开(公告)日：2007-11-27

申请号：US10248853

申请日：2003-02-25

申请人： Eric Adler ,  Serge Biesemans ,  Micah S. Galland ,  Terence B. Hook ,  Judith H. McCullen ,  Eric S. Phipps ,  James A. Slinkman

发明人： Eric Adler ,  Serge Biesemans ,  Micah S. Galland ,  Terence B. Hook ,  Judith H. McCullen ,  Eric S. Phipps ,  James A. Slinkman

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G06F17/5036 ,  G06F17/5068

摘要： A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

摘要翻译： 一种用于校正由相邻结构施加的变量的给定感兴趣结构的软件模型的方法。 首先确定相邻结构施加的变量的空间范围。 然后为空间范围分配一个值，该空间范围随着从相邻结构到给定结构的距离的函数而变化。 最后，将该值附加到给定结构的模型中。

公开(公告)号：US07166904B2

公开(公告)日：2007-01-23

申请号：US10708023

申请日：2004-02-03

申请人： Jason P. Gill ,  Terence B. Hook ,  Randy W. Mann ,  William J. Murphy ,  William R. Tonti ,  Steven H. Voldman

发明人： Jason P. Gill ,  Terence B. Hook ,  Randy W. Mann ,  William J. Murphy ,  William R. Tonti ,  Steven H. Voldman

IPC分类号： H01L29/00

CPC分类号： H01L27/11 ,  H01L27/0288 ,  H01L27/0802 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/7304 ,  H01L29/7378 ,  H01L29/7391 ,  H01L29/78 ,  Y10S257/903 ,  Y10S257/904

摘要： A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.

摘要翻译： 一种用于形成具有优异的ESD保护特性的半导体器件的方法和系统。 电阻材料层设置在触头螺柱上下表面中的至少一个上的接触孔内。 在优选实施例中，积分电阻器的电阻值介于约1欧姆至约10欧姆之间，或10欧姆至100欧姆之间。 电阻层的实施例包括溅射硅材料，隧道氧化物，隧道氮化物，硅注入氧化物，注入硅的氮化物或非晶多晶硅。 本发明的实施例包括SRAM，双极晶体管，SOI横向二极管，MOSFET和SiGe晶体管。

公开(公告)号：US07132318B2

公开(公告)日：2006-11-07

申请号：US11003988

申请日：2004-12-04

申请人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

发明人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/0251

摘要： Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

摘要翻译： 公开了一种用于改变具有绝缘体上硅（SOI）晶体管的集成电路设计的方法和结构。 该方法/结构通过在集成电路设计中跟踪电网来防止在处理到SOI晶体管的栅极期间的充电损坏，识别可能在源极/漏极和栅极之间具有电压差的SOI晶体管作为潜在损坏的SOI晶体管（基于 电网的跟踪），以及在每个潜在损坏的SOI晶体管的源极/漏极和栅极之间连接分流器件。 或者，方法/结构提供通过串联装置连接补偿导体。

公开(公告)号：US06797592B2

公开(公告)日：2004-09-28

申请号：US10421969

申请日：2003-04-23

申请人： Jeffrey S. Brown ,  Bryant C. Colwill ,  Terence B. Hook ,  Dennis Hoyniak

发明人： Jeffrey S. Brown ,  Bryant C. Colwill ,  Terence B. Hook ,  Dennis Hoyniak

IPC分类号： H01L21265

CPC分类号： H01L21/823878 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823892

摘要： A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.

摘要翻译： 提供了离子注入的方法。 该方法包括：提供衬底; 在所述基板上形成具有侧壁的掩模图像; 在衬底和掩蔽图像上形成阻挡层; 以及通过所述阻挡层进行逆向离子注入到所述衬底中，其中所述阻挡层基本上阻挡在所述掩蔽层的侧壁处散射的离子。

公开(公告)号：US06610585B1

公开(公告)日：2003-08-26

申请号：US10083062

申请日：2002-02-26

申请人： Jeffrey S. Brown ,  Bryant C. Colwill ,  Terence B. Hook ,  Dennis Hoyniak

发明人： Jeffrey S. Brown ,  Bryant C. Colwill ,  Terence B. Hook ,  Dennis Hoyniak

IPC分类号： H01L21265

CPC分类号： H01L21/823878 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823892

摘要： A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.

公开(公告)号：US6026964A

公开(公告)日：2000-02-22

申请号：US920182

申请日：1997-08-25

申请人： Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

发明人： Terence B. Hook ,  Jeffrey B. Johnson ,  Hon-Sum P. Wong

IPC分类号： H01L27/146 ,  H01L31/0352 ,  H01L31/10 ,  H01L31/14 ,  H01L31/062

CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/0352

摘要： The present invention is a active pixel sensor cell and method of making and using the same. The active pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a active pixel sensor cell circuit. Two active pixel sensor cell circuits, an NFET circuit and PFET circuit are created for use with a photodiode. The NFET circuit captures electron current. The PFET circuit captures hole current. The sum of the currents is approximately double that of conventional active pixel sensor circuits using similarly sized photodiode regions.

摘要翻译： 本发明是一种有源像素传感器单元及其制造和使用方法。 有源像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在有源像素传感器单元电路中照射光子而产生的空穴。 创建两个有源像素传感器单元电路，NFET电路和PFET电路用于光电二极管。 NFET电路捕获电子电流。 PFET电路捕获空穴电流。 电流的总和大约是使用类似尺寸的光电二极管区域的传统有源像素传感器电路的总和的两倍。

公开(公告)号：US20140061792A1

公开(公告)日：2014-03-06

申请号：US13596409

申请日：2012-08-28

申请人： Huiming Bu ,  Terence B. Hook ,  Reinaldo A. Vega

发明人： Huiming Bu ,  Terence B. Hook ,  Reinaldo A. Vega

IPC分类号： H01L29/78 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A field effect transistor device includes a bulk semiconductor substrate, a fin arranged on the bulk semiconductor substrate, the fin including a source region, a drain region, and a channel region, a first shallow trench isolation (STI) region arranged on a portion of the bulk semiconductor substrate adjacent to the fin, a first recessed region partially defined by the first STI region and the channel region of the fin, and a gate stack arranged over the channel region of the fin, wherein a portion of the gate stack is partially disposed in the first recessed region.

摘要翻译： 场效应晶体管器件包括体半导体衬底，布置在体半导体衬底上的鳍，鳍包括源极区，漏极区和沟道区，布置在部分半导体衬底上的第一浅沟槽隔离（STI）区域 邻近翅片的体半导体衬底，由第一STI区域和鳍片的沟道区域部分限定的第一凹陷区域和布置在鳍片的沟道区域上的栅极堆叠，其中栅极叠层的一部分部分地 设置在第一凹陷区域中。

公开(公告)号：US08564074B2

公开(公告)日：2013-10-22

申请号：US13306621

申请日：2011-11-29

申请人： Terence B. Hook ,  Vijay Narayanan ,  Jay M. Shah ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Helen H. Wang ,  Chendong Zhu

发明人： Terence B. Hook ,  Vijay Narayanan ,  Jay M. Shah ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Helen H. Wang ,  Chendong Zhu

IPC分类号： H01L31/119

CPC分类号： H01L21/28247 ,  H01L21/28123 ,  H01L21/76224

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.

摘要翻译： 公开了一种半导体器件。 半导体器件包括：半导体衬底，包括：高K电介质区域; 阻挡区域，其设置在所述高K电介质区域的至少一个表面上，并适于响应于暴露于氧气而形成氧化层; 以及设置在阻挡区域上的富氧区域，使得阻挡区域介于富氧区域和高K电介质区域之间。

公开(公告)号：US20130175594A1

公开(公告)日：2013-07-11

申请号：US13551714

申请日：2012-07-18

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/945

摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.