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公开(公告)号：US20140042590A1
公开(公告)日：2014-02-13
申请号：US13571441
申请日：2012-08-10
IPC分类号： H01L29/92
摘要： Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.
摘要翻译： 公开了用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法和装置。 MIM电容器可以包括电极，其可以是具有瓶颈的顶部或底部电极。 MIM电容器可以包括与通孔的侧壁接触的电极，其可以是顶部或底部电极。 当泄漏电流超过规格时，电极的侧壁接触或瓶颈可燃烧形成高阻抗路径，而电极的侧壁接触或瓶颈对于正常的MIM操作没有影响。 MIM电容器可用作去耦电容器。
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公开(公告)号：US08643074B2
公开(公告)日：2014-02-04
申请号：US13462427
申请日：2012-05-02
申请人： Chih-Yang Pai , Kuo-Chi Tu , Wen-Chuan Chiang , Chung-Yen Chou
发明人： Chih-Yang Pai , Kuo-Chi Tu , Wen-Chuan Chiang , Chung-Yen Chou
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L21/76832 , H01L21/76879 , H01L21/76897 , H01L23/5223 , H01L23/5226 , H01L23/53295 , H01L27/108 , H01L27/1085 , H01L27/10855 , H01L27/10894 , H01L28/40 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.
摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底中的隔离结构，设置在隔离结构上的导电层，设置在隔离结构上的电容器，电容器包括顶部电极，底部电极和介于 所述顶部电极和所述底部电极以及将所述导电层和所述底部电极电耦合的第一接触件，所述底部电极在至少两个面上基本接合所述第一接触。
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23.发明授权Key-hole free process for high aspect ratio gap filling with reentrant spacer 有权无缝隙工艺，用于高长宽比间隙填充可重入间隔公开(公告)号：US07482278B1
公开(公告)日：2009-01-27
申请号：US09247974
申请日：1999-02-11
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31056 , H01L21/76837
摘要： A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls of the poly pattern, further leaving a deposition of HDP-oxide on the top surface of the poly pattern. The profile of the holes within the poly pattern in such that the final layer of PE-oxide or PE-TEOS is deposited without resulting in the formation of keyholes in this latter layer.
摘要翻译： 一种沉积PE氧化物或PE-TEOS的新方法。 在多晶硅图案上提供HDP氧化物。 对沉积的HDP-氧化物进行回蚀刻，沉积一层等离子体增强的SiN。 该PE-SiN被回蚀刻，留下多边形图案的侧壁上的SiN间隔物，进一步在多晶型图案的顶表面上留下HDP氧化物。 多晶型图案中的孔的轮廓使得沉积最终的聚乙烯氧化物层或PE-TEOS层，而不会在后一层中形成键槽。
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公开(公告)号：US20080254579A1
公开(公告)日：2008-10-16
申请号：US11785023
申请日：2007-04-13
申请人： Min-Hwa Chi , Wen-Chuan Chiang , Mu-Chi Chiang , Chang-Ku Chen
发明人： Min-Hwa Chi , Wen-Chuan Chiang , Mu-Chi Chiang , Chang-Ku Chen
CPC分类号： H01L29/665 , H01L29/4991 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y02P80/30
摘要： A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap.
摘要翻译： 公开了一种用于形成半导体器件的方法。 提供了包括顺序地形成在其上的栅介电层和栅极电极层的基板。 在栅极电介质层和栅极电极层的侧壁上形成偏移间隔物。 在间隔物的侧壁上形成碳隔离物，然后除去碳隔离物。 使用栅极电极层和偏移间隔物作为掩模，注入衬底以形成轻掺杂区域。 该方法还可以包括提供具有顺序地形成在其上的栅极电介质层和栅极电极层的衬底。 衬底层形成在栅电极层的侧壁和衬底上。 在衬垫层的与栅电极层的侧壁相邻的部分上形成碳隔离物。 主间隔件形成在碳隔离件的侧壁上。 去除碳间隔物以在衬垫层和主间隔物之间形成开口。 开口由密封层密封以形成气隙。
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公开(公告)号：US06227211B1
公开(公告)日：2001-05-08
申请号：US09206740
申请日：1998-12-07
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/76816
摘要： The poor uniformity of Interlevel Dielectric Deposition (ILD) thickness for High Aspect Ratio (HAR) contact after Chemical Mechanical Planarization (CMP) will cause serious underlayer loss due to the longer over-etching time that is required to compensate for thickness differences within the wafer. Prior Art uses 1.5K Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PETEOS) to serve as a stop layer and thus reduce underlayer loss. The present invention teaches using a non-silicon oxide containing SiN/SiON or Si3N4/SiON as a stop layer. The present invention therefore is aimed at reducing underlayer loss and thereby improving the uniformity of the underlayer thickness upon completion of the hole etching process. Concurrently, the over-etch time can be reduced to less than 10% of the time required for Prior Art contact hole etching.
摘要翻译： 化学机械平面化（CMP）后高纵横比（HAR）接触的层间介电沉积（ILD）厚度差的均匀性将导致严重的底层损耗，这是由于需要更长的过蚀刻时间来补偿晶片内的厚度差异 。 现有技术使用1.5K等离子体增强四乙基 - 正硅酸盐（PETEOS）作为停止层，从而减少底层损失。 本发明教导了使用含有SiN / SiON或Si3N4 / SiON的非氧化硅作为停止层。 因此，本发明旨在减少底层损失，从而在孔蚀刻工艺完成时提高底层厚度的均匀性。 同时，过蚀刻时间可以减少到现有技术接触孔蚀刻所需时间的10％以下。
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26.发明授权Process to fabricate a cylindrical, capacitor structure under a bit line structure for a dynamic random access memory cell 失效在用于动态随机存取存储器单元的位线结构下制造圆柱形电容器结构的工艺
公开(公告)号：US6165839A
公开(公告)日：2000-12-26
申请号：US92880
申请日：1998-06-08
申请人： Yu-Hua Lee , Cheng-Ming Wu , Wen-Chuan Chiang
发明人： Yu-Hua Lee , Cheng-Ming Wu , Wen-Chuan Chiang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/91
摘要： A process for forming a DRAM, cylindrical shaped, stacked capacitor structure, located under a bit line structure, has been developed. The process features defining a polysilicon cell plate structure, during the same photolithotgraphic and anisotropic etching procedures, used to open a bit line contact hole. The bit line contact hole is formed by first opening a top portion of the bit line contact hole, using a photoresist shape as an etch mask, and after the formation of silicon nitride spacers, on the sides of the top portion of the bit line contact hole, the bottom portion of the bit line contact hole is opened, using silicon nitride as an etch mask.
摘要翻译： 已经开发了一种用于形成位于位线结构下方的DRAM，圆柱形，堆叠式电容器结构的工艺。 在用于打开位线接触孔的相同的光电影和各向异性蚀刻过程中，限定多晶硅单元板结构的过程特征。 位线接触孔通过使用光致抗蚀剂形状作为蚀刻掩模首先打开位线接触孔的顶部，并且在形成氮化硅间隔物之后，在位线接触的顶部的侧面 使用氮化硅作为蚀刻掩模，打开位线接触孔的底部。
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公开(公告)号：US09178008B2
公开(公告)日：2015-11-03
申请号：US13571441
申请日：2012-08-10
摘要： Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.
摘要翻译： 公开了用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法和装置。 MIM电容器可以包括电极，其可以是具有瓶颈的顶部或底部电极。 MIM电容器可以包括与通孔的侧壁接触的电极，其可以是顶部或底部电极。 当泄漏电流超过规格时，电极的侧壁接触或瓶颈可燃烧形成高阻抗路径，而电极的侧壁接触或瓶颈对于正常的MIM操作没有影响。 MIM电容器可用作去耦电容器。
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公开(公告)号：US20120091559A1
公开(公告)日：2012-04-19
申请号：US13267424
申请日：2011-10-06
申请人： Kuo-Chi Tu , Wen-Chuan Chiang , Chen-Jong Wang
发明人： Kuo-Chi Tu , Wen-Chuan Chiang , Chen-Jong Wang
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.
摘要翻译： 片上系统（SOC）装置包括第一区域中的第一电容器，第二区域中的第二电容器，以及可以在第三区域中包括第三电容器，以及附加区域中的任何附加数量的电容器。 电容器可以具有不同的形状和尺寸。 区域可以包括多于一个的电容器。 区域中的每个电容器具有顶部电极，底部电极和电容器绝缘体。 所有电容器的顶部电极以公共工艺形成，而所有电容器的底部电极形成在共同的工艺中。 电容绝缘体可以具有不同数量的子层，形成不同的材料或不同的厚度。 电容器可以形成在层间电介质层中或在金属间介电层中。 这些区域可以是混合信号区域，模拟区域，射频区域，动态随机存取存储区域等。
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公开(公告)号：US07633110B2
公开(公告)日：2009-12-15
申请号：US10945762
申请日：2004-09-21
申请人： Min-Hwa Chi , Wen-Chuan Chiang , Cheng-Ku Chen
发明人： Min-Hwa Chi , Wen-Chuan Chiang , Cheng-Ku Chen
IPC分类号： H01L27/108
CPC分类号： H01L27/10805 , H01L27/10829 , H01L27/1085
摘要： Disclosed herein is a DRAM memory cell featuring a reduced size, increased retention time, and compatibility with standard logic manufacturing processes, making it well-suited for use as embedded DRAM. The memory cell disclosed herein includes a pass-gate transistor and a storage region. The transistor includes a gate and a drain. The storage region includes a trench, which is preferably a Shallow Trench Isolation (STI). A non-insulating structure, e.g., formed of polysilicon or metal, is located in the trench as serves as a capacitor node. The trench is partially defined by a doped sidewall that serves as a source for the transistor. The poly structure and the trench sidewall are separated by a dielectric layer. The write operation involves charge transport to the non-insulating structure by direct tunneling through the dielectric layer. The read operation is assisted by Gate Induced Drain Leakage (GIDL) current generated on the surface of the sidewall.
摘要翻译： 这里公开了一种具有减小的尺寸，增加的保留时间以及与标准逻辑制造工艺的兼容性的DRAM存储单元，使其非常适合用作嵌入式DRAM。 本文公开的存储单元包括通过栅极晶体管和存储区域。 晶体管包括栅极和漏极。 存储区域包括沟槽，其优选地是浅沟槽隔离（STI）。 例如由多晶硅或金属形成的非绝缘结构位于沟槽中作为电容器节点。 沟槽部分地由用作晶体管的源极的掺杂侧壁限定。 多晶硅结构和沟槽侧壁被介电层分开。 写入操作涉及通过直接穿过介电层的隧道将电荷传输到非绝缘结构。 读取操作由在侧壁表面产生的栅极引入漏极泄漏（GIDL）电流辅助。
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公开(公告)号：US07564105B2
公开(公告)日：2009-07-21
申请号：US11094879
申请日：2005-03-30
申请人： Min-Hwa Chi , Wen-Chuan Chiang , Mu-Chi Chiang
发明人： Min-Hwa Chi , Wen-Chuan Chiang , Mu-Chi Chiang
IPC分类号： H01L27/088
CPC分类号： H01L29/7853 , H01L29/66795
摘要： The types of quasi-planar CMOS and FinFET-like transistor devices on a bulk silicon substrate are disclosed. A first device has a doped and recessed channel formed in a shallow trench sidewall. A second device has a doped, recessed channel and has a plurality of edge-fins juxtaposed on an edge of an active region of the device. A third device has an undoped recessed channel formed in a sidewall of a shallow trench, wherein the undoped recessed channel further has a plurality of edge-fins disposed thereon. Additionally, an extra mask may be added to each device to allow for fabrication of both conventional transistors and FinFET-like transistors on bulk silicon. The extra mask may protect the source and drain areas from recess etching of the silicon substrate. Several methods of fabricating each device are also disclosed.
摘要翻译： 公开了在体硅衬底上的准平面CMOS和FinFET类晶体管器件的类型。 第一器件具有形成在浅沟槽侧壁中的掺杂和凹陷沟道。 第二装置具有掺杂的凹陷通道，并且具有并置在装置的有源区域的边缘上的多个边缘鳍片。 第三装置具有形成在浅沟槽的侧壁中的未掺杂的凹陷通道，其中未掺杂的凹陷通道还具有设置在其上的多个边缘翅片。 此外，可以向每个器件添加额外的掩模，以允许在体硅上制造常规晶体管和FinFET类晶体管。 额外的掩模可以保护源极和漏极区域免受硅衬底的凹陷蚀刻。 还公开了制造每个器件的几种方法。
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