公开(公告)号：US06964910B2

公开(公告)日：2005-11-15

申请号：US10612839

申请日：2003-07-03

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/768 ,  G11C11/24 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10852 ,  G11C11/24 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10855

摘要： Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays are described. In one embodiment, a conductive capacitor plug is formed to extend from proximate a substrate node location to a location elevationally above all conductive material of an adjacent bit line. In another embodiment, a capacitor contact opening is etched through a first insulative material received over a bit line and a word line substantially selective relative to a second insulative material covering portions of the bit line and the word line. The opening is etched to a substrate location proximate the word line in a self-aligning manner relative to both the bit line and the word line. In another embodiment, capacitor contact openings are formed to elevationally below the bit lines after the bit lines are formed. In a preferred embodiment, capacitor-over-bit line memory arrays are formed.

摘要翻译： 描述形成导电电容器插头的方法，形成电容器接触开口的方法以及形成存储器阵列的方法。 在一个实施例中，导电电容器插头被形成为从邻近的衬底节点位置延伸到相邻位线的所有导电材料的正上方的位置。 在另一个实施例中，电容器接触开口被蚀刻通过位线和基本上选择性相对于覆盖位线和字线部分的第二绝缘材料的字线接收的第一绝缘材料。 以相对于位线和字线两者的自对准方式将开口蚀刻到靠近字线的衬底位置。 在另一个实施例中，在形成位线之后，电容器接触开口形成在位线的正下方。 在一个优选的实施例中，形成了电容器对位线行存储器阵列。

公开(公告)号：US06875646B2

公开(公告)日：2005-04-05

申请号：US10264615

申请日：2002-10-03

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/8234 ,  H01L21/00

CPC分类号： H01L21/823412 ,  H01L21/823425 ,  H01L27/1052 ,  H01L27/10894

摘要： Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.

摘要翻译： 描述形成集成电路的半导体处理方法。 在一个实施例中，在衬底上形成存储器电路和外围电路。 外围电路包括第一和第二类型的MOS晶体管。 在比第一类型的所有外围MOS晶体管少的情况下，将第二类型的晕轮植入物导入第一类型的MOS晶体管。 在另一个实施例中，多个n型晶体管器件形成在衬底上并且包括存储器阵列电路和外围电路。 至少一些单独的外围电路n型晶体管器件被部分屏蔽，并且对部分屏蔽的外围电路n型晶体管器件的未屏蔽部分进行晕圈注入。 在另一个实施例中，源极和漏极区域中的仅一个区域的至少一部分被掩蔽，并且源极和漏极区域中的另一个的至少一部分被暴露用于至少一些外围电路n型晶体管器件 。 相对于源极和漏极区域的暴露部分进行晕轮植入。 在另一个实施例中，使用公共屏蔽步骤，并且在衬底上形成的器件进行晕轮注入，该器件包括存储器电路和外围电路，其足以赋予器件中的至少三个器件三个不同的相应阈值电压。

公开(公告)号：US06803278B2

公开(公告)日：2004-10-12

申请号：US10280757

申请日：2002-10-24

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21336

CPC分类号： H01L27/10873 ,  H01L27/0214 ,  H01L27/10894 ,  Y10S257/906 ,  Y10S438/981

摘要： The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.

摘要翻译： 本发明包括形成在半导体衬底上的6F 2 DRAM阵列。 存储器阵列包括第一存储单元。 第一存储单元包括第一存取晶体管和第一数据存储电容器。 第一存取晶体管的第一负载电极经由形成在衬底上的第一存储节点耦合到第一数据存储电容器。 存储器阵列还包括第二存储器单元。 第二存储单元包括第二存取晶体管和第二数据存储电容器。 第二存取晶体管的第一负载电极经由形成在基板上的第二存储节点耦合到第二数据存储电容器。 第一和第二存取晶体管具有具有第一厚度的栅极电介质。 存储器阵列还包括形成在第一和第二存储节点之间并被配置为在它们之间提供电隔离的隔离栅极。 隔离栅极具有第二厚度大于第一厚度的栅极电介质。 隔离栅极电介质可以在衬底的表面上方或下方延伸。

公开(公告)号：US06784502B2

公开(公告)日：2004-08-31

申请号：US09512978

申请日：2000-02-24

申请人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L2976

CPC分类号： H01L27/10897 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/10891 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.

摘要翻译： 描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。 在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。 单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。 绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。 导电触点形成在接触开口内并与各个接触垫电连接。 在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。 在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

公开(公告)号：US06747326B2

公开(公告)日：2004-06-08

申请号：US10302965

申请日：2002-11-25

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L2978

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1083

摘要： A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.

摘要翻译： 一种用于调节Vt同时最小化低电压高速半导体器件的寄生电容的方法。 该方法使用阴影效应和倾斜冲击穿过垂直结构之间的预防植入物来提供分级植入物。 植入角度大于或等于S / H的反正切，其中S是水平距离，H是这种垂直结构的高度。

公开(公告)号：US06380023B2

公开(公告)日：2002-04-30

申请号：US09146115

申请日：1998-09-02

申请人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L218234

CPC分类号： H01L27/10897 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/10891 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.

摘要翻译： 描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。 在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。 单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。 绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。 导电触点形成在接触开口内并与各个接触垫电连接。 在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。 在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

公开(公告)号：US06312997B1

公开(公告)日：2001-11-06

申请号：US09132904

申请日：1998-08-12

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21336

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1083

摘要： A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.

公开(公告)号：US06215151B1

公开(公告)日：2001-04-10

申请号：US09255667

申请日：1999-02-23

申请人： Zhiqiang Wu ,  Luan C. Tran ,  Robert Kerr ,  Shubneesh Batra ,  Rongsheng Yang

发明人： Zhiqiang Wu ,  Luan C. Tran ,  Robert Kerr ,  Shubneesh Batra ,  Rongsheng Yang

IPC分类号： H01L27148

CPC分类号： H01L21/823807

摘要： Integrated circuitry and methods of forming integrated circuitry are described. In one implementation, a common masking step is utilized to provide source/drain diffusion regions and halo ion implantation or dopant regions relative to the source/drain regions within one well region of a substrate; and well contact diffusion regions within another well region of the substrate. The common masking step preferably defines at least one mask opening over the substrate within which the well contact diffusion region is to be formed, and the mask opening is suitably dimensioned to reduce the amount of halo ion implantation dopant which ultimately reaches the substrate therebelow. According to one aspect, a plurality of mask openings are provided. According to another aspect, a suitably-dimensioned single mask opening is provided. In yet another aspect, a unique well region construction is provided with one or more complementary mask openings which is (are) configured to, in connection with the provision of the halo ion implantation dopant, block the amount of implantation dopant which ultimately reaches the substrate adjacent the well contact diffusion regions. Accordingly, at least some of the well contact diffusion region(s) remain in substantial contact with the well region after the doping of the substrate with the halo ion implantation dopant.

摘要翻译： 描述了形成集成电路的集成电路和方法。 在一个实现中，利用公共掩模步骤来相对于衬底的一个阱区域内的源极/漏极区域提供源极/漏极扩散区域和晕圈离子注入或掺杂区域; 以及在衬底的另一个阱区域内的良好接触扩散区域。 常见的掩蔽步骤优选地限定在其上将要形成阱接触扩散区的衬底上的至少一个掩模开口，并且掩模开口被适当地设定尺寸以减少最终到达衬底的卤素离子注入掺杂剂的量。 根据一个方面，提供了多个掩模开口。 根据另一方面，提供了适当尺寸的单个掩模开口。 在另一方面，独特的井区结构设置有一个或多个互补掩模开口，其被配置为与提供卤素离子注入掺杂剂相结合，阻止最终到达衬底的注入掺杂剂的量 邻近阱接触扩散区。 因此，在用卤素离子注入掺杂剂掺杂衬底之后，至少一些阱接触扩散区域保持与阱区基本接触。

公开(公告)号：US6159790A

公开(公告)日：2000-12-12

申请号：US310489

申请日：1999-05-12

申请人： Fernando Gonzalez ,  D. Mark Durcan ,  Luan C. Tran ,  Robert B. Kerr ,  David F. Cheffings ,  Howard E. Rhodes

发明人： Fernando Gonzalez ,  D. Mark Durcan ,  Luan C. Tran ,  Robert B. Kerr ,  David F. Cheffings ,  Howard E. Rhodes

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L28/82

摘要： A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.

摘要翻译： 用于控制来自三维膜的向外扩散量的固态制造技术包括以限定上部和下部的方式提供第一层原位掺杂膜的步骤。 第二层未掺杂的膜设置在第一层的顶部上，以类似地限定上部和下部。 根据预定图案蚀刻第一层和第二层。 掺杂第二层以获得从上部向下部减小的期望的掺杂剂密度。 从第二层的上部扩散掺杂剂导致掺杂剂迁移到第二层的下部。 因此，消除或大大降低了向基板的扩散和由此引起的问题。

公开(公告)号：US08980756B2

公开(公告)日：2015-03-17

申请号：US11830449

申请日：2007-07-30

申请人： Luan C. Tran ,  Raghupathy Giridhar

发明人： Luan C. Tran ,  Raghupathy Giridhar

IPC分类号： H01L21/461 ,  H01L21/3213 ,  H01L21/033 ,  H01L27/105

CPC分类号： H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/1052

摘要： Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

摘要翻译： 用于通过反向间距减小流程进行器件制造的方法的实施例包括在形成第一特征图案之后形成衬底上方的特征的第一图案并形成间距倍数间隔物的第二图案。 在本发明的实施例中，可以通过光刻形成第一特征图案，并且可以通过间距倍增形成间距倍增间隔物的第二图案。 提供了其他用于器件制造的方法。