利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

86 条记录 (耗时 0.019 秒)

    Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials
    21.
    发明申请
    Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials 有权
    具有NMOS高k电介质的半导体CMOS器件和方法存在于芯区中，可减轻介电材料的损坏

    公开(公告)号：US20060246651A1

    公开(公告)日：2006-11-02

    申请号：US11118843

    申请日：2005-04-29

    申请人： James Chambers ,  Mark Visokay ,  Luigi Colombo

    发明人： James Chambers ,  Mark Visokay ,  Luigi Colombo

    IPC分类号： H01L21/8238 ,  H01L21/8234

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

    摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

    Refractory metal-based electrodes for work function setting in semiconductor devices
    23.
    发明申请
    Refractory metal-based electrodes for work function setting in semiconductor devices 有权
    用于半导体器件功能设置的耐火金属基电极

    公开(公告)号：US20050258500A1

    公开(公告)日：2005-11-24

    申请号：US10852523

    申请日：2004-05-24

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L21/3205 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L21/823842 ,  H01L29/4958

    摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

    摘要翻译： 本发明在一个实施例中提供一种栅极结构（100）。 栅极结构包括栅极电介质（105）和栅极（110）。 栅极电介质包括难熔金属并且位于半导体衬底（115）之上。 半导体衬底具有导带和价带。 栅极位于栅极电介质上方并且包括难熔金属。 栅极具有与导带或价带对准的功函数。 其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。

    Dual work function metal gate integration in semiconductor devices
    24.
    发明申请
    Dual work function metal gate integration in semiconductor devices 有权
    双功能金属门集成在半导体器件中

    公开(公告)号：US20050258468A1

    公开(公告)日：2005-11-24

    申请号：US10890365

    申请日：2004-07-13

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L21/3205 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L21/823842 ,  H01L29/4958

    摘要： The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).

    摘要翻译： 本发明在一个实施例中提供了一种用于形成双功函数金属栅极半导体器件（100）的工艺。 该方法包括提供其上具有栅极电介质层（110）的半导体衬底（105）和栅极电介质层上的金属层（205）。 金属层的功函数与半导体衬底的导带或价带相匹配。 该方法还包括在金属层的一部分（215）和金属层上的材料层（305）上形成导电阻挡层（210）。 对金属层和材料层进行退火以形成金属合金层（405），从而将金属合金层的功函数与衬底的导带或价带中的另一个相匹配。 本发明的其它实施例包括双功函数金属栅极半导体器件（900）和集成电路（1000）。

    Metal gate MOS transistors and methods for making the same
    25.
    发明申请
    Metal gate MOS transistors and methods for making the same 有权
    金属栅极MOS晶体管及其制造方法

    公开(公告)号：US20050059198A1

    公开(公告)日：2005-03-17

    申请号：US10661130

    申请日：2003-09-12

    申请人： Mark Visokay ,  Luigi Colombo ,  James Chambers

    发明人： Mark Visokay ,  Luigi Colombo ,  James Chambers

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L21/44 ,  H01L29/76

    CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

    摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal boride is formed above a gate dielectric to create PMOS gate structures and metal nitride is formed over a gate dielectric to provide NMOS gate structures. The metal portions of the gate structures are formed from an initial starting material that is either a metal boride or a metal nitride, after which the starting material is provided with boron or nitrogen in one of the PMOS and NMOS regions through implantation, diffusion, or other techniques, either before or after formation of the conductive upper material, and before or after gate patterning. The change in the boron or nitrogen content of the starting material provides adjustment of the material work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.

    摘要翻译： 提供了半导体器件和制造方法，其中为MOS晶体管提供金属晶体管栅极。 金属硼化物形成在栅极电介质上方以产生PMOS栅极结构，并且在栅极电介质上形成金属氮化物以提供NMOS栅极结构。 栅极结构的金属部分由起始原料是金属硼化物或金属氮化物形成，之后起始材料通过注入，扩散或扩散形成在PMOS和NMOS区域之一中的硼或氮中。 在形成导电上部材料之前或之后以及栅极图案化之前或之后的其它技术。 起始材料的硼或氮含量的变化提供材料功函数的调整，从而调谐所得PMOS或NMOS晶体管的阈值电压。

    Work function separation for fully silicided gates
    26.
    发明申请
    Work function separation for fully silicided gates 审中-公开
    完全硅化栅的工作功能分离

    公开(公告)号：US20070037333A1

    公开(公告)日：2007-02-15

    申请号：US11203716

    申请日：2005-08-15

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823835 ,  H01L21/823842

    摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal is added to a first region of polysilicon overlying a dielectric that is on a substrate, and a second metal is added to a second region of the polysilicon. A third metal is formed over the first and second regions and a silicidation process if performed to form a first alloy in the first region and a second alloy in the second region. First and second segregated regions are also established adjacent to the dielectric in the first and second regions, respectively. The first and second metals serve to shift or adjust respective values of first and second work functions in the first and second regions.

    摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，将第一金属添加到覆盖在衬底上的电介质上的多晶硅的第一区域中，并且将第二金属添加到多晶硅的第二区域。 在第一和第二区域上形成第三金属，如果在第一区域中形成第一合金并且在第二区域中形成第二合金，则形成硅化工艺。 第一和第二分离区域也分别在第一和第二区域中的电介质附近建立。 第一和第二金属用于移动或调整第一和第二区域中的第一和第二功函数的相应值。

    Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon
    27.
    发明申请
    Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon 有权
    半导体CMOS器件和方法与NMOS高k电介质之间形成核心PMOS氮氧化硅介质形成之前，采用直接氮化硅

    公开(公告)号：US20060246647A1

    公开(公告)日：2006-11-02

    申请号：US11118842

    申请日：2005-04-29

    申请人： Mark Visokay ,  Luigi Colombo ,  James Chambers

    发明人： Mark Visokay ,  Luigi Colombo ,  James Chambers

    IPC分类号： H01L21/8238 ,  H01L21/8242

    CPC分类号： H01L27/105 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/11 ,  H01L27/1116

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A silicon nitride layer is grown (516) within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed (518) that oxidizes the silicon nitride into silicon oxynitride.

    摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成氧化物层。 氧化物层从器件的核心区域移除（508）。 在芯和I / O区域上形成高k电介质层（510）。 然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。 通过低温热处理在核心和I / O区域的PMOS区域内生长氮化硅层（516）。 随后，进行氧化处理（518），其将氮化硅氧化成氮氧化硅。

    REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES
    29.
    发明申请
    REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20060273414A1

    公开(公告)日：2006-12-07

    申请号：US11465219

    申请日：2006-08-17

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L29/94

    CPC分类号： H01L21/823842 ,  H01L29/4958

    摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

    Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation
    30.
    发明申请
    Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation 有权
    半导体CMOS器件和方法，在核心PMOS电介质形成之前形成NMOS高k电介质

    公开(公告)号：US20060246716A1

    公开(公告)日：2006-11-02

    申请号：US11118237

    申请日：2005-04-29

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/823857 ,  H01L27/11

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.

    摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成第一氧化物层。 第一氧化物层从器件的核心区域移除（508）。 在芯和I / O区域上形成高k电介质层（510）。 然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。 在芯和I / O区域的NMOS区域内形成第二氧化物层（516），并且执行氮化处理（518），其氮化第二氧化物层和高k电介质层。