公开(公告)号：US20170308463A1

公开(公告)日：2017-10-26

申请号：US15139252

申请日：2016-04-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

IPC: G06F12/06

CPC classification number: G06F12/0623 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/2022 ,  G11C16/08

Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

公开(公告)号：US20160292031A1

公开(公告)日：2016-10-06

申请号：US15185066

申请日：2016-06-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Feng Cheng ,  Yu-Chen Wang ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: G06F11/10 ,  G11C11/56 ,  G11C16/14

CPC classification number: G06F11/1044 ,  G06F11/1068 ,  G06F11/1076 ,  G06F2212/403 ,  G11C11/5635 ,  G11C16/00 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C29/42

Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.

公开(公告)号：US09417640B2

公开(公告)日：2016-08-16

申请号：US14274237

申请日：2014-05-09

Applicant: Macronix International Co., Ltd.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang ,  Chao-Hsin Lin

IPC: H03K17/22 ,  G05F1/46

CPC classification number: G05F1/46 ,  G05F1/468 ,  H03K17/22

Abstract: An integrated circuit device includes a pad adapted to receive a signal from an external driver. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may correspond to a logic low level or a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the voltage level in response to an event that causes the initialization.

Abstract translation: 集成电路器件包括适于从外部驱动器接收信号的焊盘。 状态寄存器被编程为响应于该焊盘的状态而指示在集成电路器件的电路初始化期间为焊盘设置的电压电平的状态。 电压电平可以对应于逻辑低电平或逻辑高电平。 电压保持电路耦合到焊盘和状态寄存器，并且被配置为响应于引起初始化的事件而迫使焊盘达到电压电平。

公开(公告)号：US09400712B2

公开(公告)日：2016-07-26

申请号：US14160612

申请日：2014-01-22

Applicant: Macronix International Co., Ltd.

Inventor： Chin-Hung Chang ,  Chia-Feng Cheng ,  Yu-Chen Wang ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: G11C29/00 ,  G06F11/10 ,  G11C16/16 ,  G11C29/42 ,  G11C16/00

CPC classification number: G06F11/1044 ,  G06F11/1068 ,  G06F11/1076 ,  G06F2212/403 ,  G11C11/5635 ,  G11C16/00 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C29/42

Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.

Abstract translation: 提供了一种存储器件的擦除方法。 存储器件包括存储器控制器和具有第一存储器区域和第二存储器区域的存储器阵列。 第一存储器区域和第二存储器区域共享相同的阱。 擦除方法包括以下步骤：擦除第一存储区; 以及根据纠错码算法有选择地对第二存储区进行编程。

公开(公告)号：US20150213864A1

公开(公告)日：2015-07-30

申请号：US14162854

申请日：2014-01-24

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Yu-Chen Wang ,  Chin-Hung Chang ,  Chia-Feng Cheng ,  Min-Hsiung Meng

IPC: G11C8/18

CPC classification number: G11C8/18 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/0409

Abstract: A method and a system for operating a memory are provided. The memory includes a plurality of memory cells which are configured to store data. The method includes the following steps. A counting number recorded in a counter is counted by 1, if the memory is written. The memory is set as a frequently using device, if the counting number recoded in the counter reaches a predetermined value.

Abstract translation: 提供了一种用于操作存储器的方法和系统。 存储器包括被配置为存储数据的多个存储单元。 该方法包括以下步骤。 如果存储器被写入，计数器中记录的计数器被计数1。 如果在计数器中重新编码的计数号达到预定值，则将存储器设置为频繁使用的设备。

公开(公告)号：US12136471B2

公开(公告)日：2024-11-05

申请号：US18231611

申请日：2023-08-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: G11C7/24 ,  G06F21/44 ,  H04L9/32

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

公开(公告)号：US12086414B2

公开(公告)日：2024-09-10

申请号：US17961176

申请日：2022-10-06

Applicant: Macronix International Co., Ltd.

Inventor： Chin-Hung Chang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G06F3/06 ,  G11C15/04

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G11C15/04

Abstract: Systems, devices, methods, and circuits for managing content addressable memory (CAM) devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in memory cells, and a circuitry coupled to the memory cell array and configured to execute a search operation in the memory cell array according to a search instruction. The search instruction includes at least one of search data or an option code, and the option code specifies, for the search operation, at least one of a search length or a search depth.

公开(公告)号：US20240184668A1

公开(公告)日：2024-06-06

申请号：US18191401

申请日：2023-03-28

Applicant: Macronix International Co., Ltd.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: Systems, devices, methods, and circuits for managing status output are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation. The read packet includes readout data and error information associated with the readout data. The error information is indicated by at least one of an error code or one or more secure codes in the read packet.

公开(公告)号：US11601269B2

公开(公告)日：2023-03-07

申请号：US17143097

申请日：2021-01-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Chin-Hung Chang

IPC: H04L9/08 ,  H04L9/32 ,  G06F12/14 ,  G11C7/24 ,  G09C1/00 ,  G11C16/22 ,  G06F12/02 ,  H03K19/003 ,  G11C7/10 ,  G11C8/20 ,  G11C16/04

Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

公开(公告)号：US11380379B2

公开(公告)日：2022-07-05

申请号：US17087085

申请日：2020-11-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: G11C7/24 ,  H04L9/32 ,  G06F21/44

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.