公开(公告)号：US20170147217A1

公开(公告)日：2017-05-25

申请号：US15093841

申请日：2016-04-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Yu-Ming Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06 ,  G11C16/34 ,  G11C16/10

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3427 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.

公开(公告)号：US09478288B1

公开(公告)日：2016-10-25

申请号：US14687998

申请日：2015-04-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Win-San Khwa ,  Tzu-Hsiang Su ,  Chao-I Wu ,  Hsiang-Pang Li ,  Yu-Ming Chang

IPC: G11C16/04 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/77

Abstract: A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.

Abstract translation: 一种用于编程存储器件的方法包括以下步骤：执行交织编程，包括：在第一时间间隔期间对第一存储器单元进行编程，并在第二时间间隔内相应地验证第一存储器单元; 在第三时间间隔期间编程第二存储器单元，并在第一和第二时间间隔之间的第四时间间隔期间相应地验证第二存储器单元; 以及在所述第一和第二时间间隔之间插入至少一个虚拟周期，以确保所述第一存储单元的每单位时间的电阻变化小于阈值。

公开(公告)号：US20160307627A1

公开(公告)日：2016-10-20

申请号：US14687998

申请日：2015-04-16

Applicant: Macronix International Co., Ltd.

Inventor： Win-San Khwa ,  Tzu-Hsiang Su ,  Chao-I Wu ,  Hsiang-Pang Li ,  Yu-Ming Chang

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/77

Abstract: A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.

Abstract translation: 一种用于编程存储器件的方法包括以下步骤：执行交织编程，包括：在第一时间间隔期间对第一存储器单元进行编程，并在第二时间间隔内相应地验证第一存储器单元; 在第三时间间隔期间编程第二存储器单元，并在第一和第二时间间隔之间的第四时间间隔期间相应地验证第二存储器单元; 以及在所述第一和第二时间间隔之间插入至少一个虚拟周期，以确保所述第一存储单元的每单位时间的电阻变化小于阈值。

公开(公告)号：US10007446B2

公开(公告)日：2018-06-26

申请号：US14703941

申请日：2015-05-05

Applicant: Macronix International Co., Ltd.

Inventor： Wei-Chieh Huang ,  Li-Chun Huang ,  Yu-Ming Chang ,  Hung-Sheng Chang ,  Hsiang-Pang Li ,  Ting-Yu Liu ,  Chien-Hsin Liu ,  Nai-Ping Kuo

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/067 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/1024 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.

公开(公告)号：US09627072B2

公开(公告)日：2017-04-18

申请号：US14857598

申请日：2015-09-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: A multiple-bit-per-cell, page mode memory comprises a plurality of physical pages, each physical page having N addressable pages p(n). Logic implements a plurality of selectable program operations to program an addressed page. Logic select one of the plurality of selectable program operations to program an addressed page in the particular physical page using a signal that indicates a logical status of another addressable page in the particular physical page. The logical status can indicate whether the other addressable page contains invalid data. The first program operation overwrites the other addressable page, and the second program operation preserves the other addressable page. The first program operation can execute more quickly than the second program operation. The logic can also be applied for programming multiple-bit-per-cell memory not configured in a page mode.

公开(公告)号：US09025375B2

公开(公告)日：2015-05-05

申请号：US14060296

申请日：2013-10-22

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C16/04 ,  G11C16/34 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。