公开(公告)号：US11621702B2

公开(公告)日：2023-04-04

申请号：US17557204

申请日：2021-12-21

Applicant: Microchip Technology Incorporated

Inventor： Yong Yuenyongsgool ,  Stephen Bowling ,  Pedro Ovalle

IPC: H03K3/017 ,  G06F1/06 ,  H03K21/02

Abstract: An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

公开(公告)号：US10515036B2

公开(公告)日：2019-12-24

申请号：US16169480

申请日：2018-10-24

Applicant: Microchip Technology Incorporated

Inventor： Yong Yuenyongsgool ,  Stephen Bowling ,  Cobus van Eeden ,  Igor Wojewoda ,  Naveen Raj

IPC: G06F13/28 ,  G06F13/16 ,  G06F9/30 ,  G06F13/40

Abstract: A memory management circuit includes a direct memory access (DMA) channel. The DMA channel includes logic configured to receive a buffer of data to be written using DMA. The DMA channel further includes logic to perform bit manipulation in real-time during a DMA write cycle of the first buffer of data.

公开(公告)号：US20190113568A1

公开(公告)日：2019-04-18

申请号：US15785792

申请日：2017-10-17

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Igor Wojewoda ,  Dereck Fernandes ,  Manivannan Balu ,  Yong Yuenyongsgool ,  Timothy Phoenix ,  Steve Bradley

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31724 ,  G01R31/31723 ,  G01R31/3177 ,  G11C29/14 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/0401 ,  G11C2029/0409

Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.

公开(公告)号：US20190094905A1

公开(公告)日：2019-03-28

申请号：US16143967

申请日：2018-09-27

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Igor Wojewoda ,  Stephen Bowling ,  Yong Yuenyongsgool

IPC: G06F1/08 ,  G06F1/20 ,  G06F11/30 ,  G01R23/15 ,  G01R19/25 ,  G05B13/02

Abstract: A temperature-compensating clock frequency monitor circuit may be provided to detect a clock pulse frequency in an electronic device that may cause erratic or dangerous operation of the device, as a function of an operating temperature of the device. The temperature-compensating clock frequency monitor circuit include a temperature sensor configured to measure a temperature associated with an electronic device, a clock having an operating frequency, and a frequency monitoring system. The frequency monitoring system may be configured to determine the operating frequency of the clock, and based at least on (a) the operating frequency of the clock and (b) the measured temperature associated with the electronic device, generate a corrective action signal to initiate a corrective action associated with the electronic device or a related device. The temperature sensor, clock, and frequency monitoring system may, for example, be provided on a microcontroller.

公开(公告)号：US09602895B2

公开(公告)日：2017-03-21

申请号：US14538253

申请日：2014-11-11

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Michael Simmons

IPC: H04Q9/00 ,  G01R22/06 ,  G08B13/00

CPC classification number: H04Q9/00 ,  G01R22/066 ,  G08B13/00

Abstract: If an enclosure of a metering device is opened or vandalized, application software must determine when the metering history information became unreliable, and further notification to the utility may be desirable. Likewise, a shipping container or suitcase that has been opened or mishandled during shipping transient may be attributed to a particular location and/or handling person(s) when the time and date of the mishandling occurrence are known. A transition on a special device input from a tamper or mishandling sensor captures real-time clock/calendar (RTCC) information that provides to a software application the time and date of the detected tampering or mishandling event. This transition may also cause memory storage of the RTCC information related to the event. Thus, an integrated circuit device, for example a microcontroller or any other integrated circuit device may comprise such an RTCC and external input, and, optionally, memory storage of the RTCC event occurrence.

公开(公告)号：US20160269016A1

公开(公告)日：2016-09-15

申请号：US15064843

申请日：2016-03-09

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Stephen Bowling ,  Alex Dumais

IPC: H03K7/08 ,  H02M1/08

CPC classification number: H03K7/08 ,  H02M1/08 ,  H02M3/157 ,  H02M2001/0012

Abstract: A number of standard PWM generators produce PWM signals that may be used to drive the power stages for Full-Bridge, Feed-Forward, Push-Pull, Phase-Shift Zero Voltage Transition (ZVT), and other switched mode power supply (SMPS) conversion topologies. These PWM signals may be fed to logic functions of a combinatorial logic block. Appropriate PWM signals are selected as operands along with desired logic function(s) that operates on these input operands. The resultant combinatorial PWM signals may then be used directly or may be fed through dead-time processing circuitry prior to outputting to an application circuit. In addition to the combinatorial logic functions, sequential logic functions may also be used to provide sequential PWM signals, e.g., synchronous sequential, asynchronous sequential, and/or sequential-combinatorial PWM signals.

Abstract translation: 许多标准PWM发生器产生可用于驱动全桥，前馈，推挽，相移零电压转换（ZVT）和其他开关模式电源（SMPS）的功率级的PWM信号， 转换拓扑。 这些PWM信号可以被馈送到组合逻辑块的逻辑功能。 选择适当的PWM信号作为操作数以及对这些输入操作数进行操作的所需逻辑功能。 所得到的组合PWM信号可以直接使用，或者可以在输出到应用电路之前通过死区时间处理电路馈送。 除了组合逻辑功能之外，顺序逻辑功能还可用于提供顺序PWM信号，例如同步顺序，异步顺序和/或顺序组合PWM信号。

公开(公告)号：US09201446B2

公开(公告)日：2015-12-01

申请号：US13753341

申请日：2013-01-29

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  James Bartling

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/14

CPC classification number: G06F1/06 ,  G06F1/04 ,  G06F1/14

Abstract: A microcontroller has a programmable timebase, wherein the timebase has a trigger input to start a timer or counter of the timebase and wherein the timebase can be configured to operate upon receiving a trigger signal in a first mode to generate a plurality of timer/counter event signals until a reset bit in a control register is set and in a second mode to generate a single timer/counter event signal and wherein the timebase can be configured to operate in a third mode to generate a predefined number of timer/counter event signals, wherein the predefined number is defined by a plurality of bits of a register.

Abstract translation: 微控制器具有可编程时基，其中所述时基具有触发输入以启动所述时基的定时器或计数器，并且其中所述时基可被配置为在以第一模式接收到触发信号时操作以产生多个定时器/计数器事件 直到控制寄存器中的复位位置1，并且在第二模式中产生单个定时器/计数器事件信号，并且其中该时基可被配置为在第三模式中操作以产生预定数量的定时器/计数器事件信号， 其中预定数量由寄存器的多个位来定义。

公开(公告)号：US20140254731A1

公开(公告)日：2014-09-11

申请号：US14197812

申请日：2014-03-05

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Samar Naik ,  Igor Wojewoda

IPC: H04L7/00

CPC classification number: H04L7/0079 ,  H04L7/0331 ,  H04L7/044 ,  H04L25/49 ,  H04L25/4902

Abstract: A system for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT and wherein a receiver is operated by system clock, includes: a clock divider for dividing the system clock by M, wherein M evenly divides N, and a detector for sampling a received data nibble length by using a dithered sampling clock.

Abstract translation: 一种用于确定串行传输协议的单位时间的系统，其中所述串行传输协议通过发送具有预定长度的N * UT的校准脉冲来定义单位时间（UT），并且其中接收机由系统时钟操作，包括： 用于将系统时钟除以M的时钟分频器，其中M均匀地划分N，以及用于使用抖动采样时钟对接收数据半字节长度进行采样的检测器。

公开(公告)号：US20140240020A1

公开(公告)日：2014-08-28

申请号：US13778436

申请日：2013-02-27

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Bryan Kris ,  John Day ,  Alex Dumais ,  Stephen Bowling

IPC: H03K5/13

CPC classification number: H03K5/133 ,  H02M1/08 ,  H02M1/32 ,  H02M1/38 ,  H02M3/3353 ,  H02M3/33576

Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

Abstract translation: 多个PWM发生器具有用于由其产生的每个PWM控制信号的用户可配置的时间延迟电路。 时间延迟电路被调整，使得每个PWM控制信号同时到达它们相关联的功率晶体管。 这可以通过确定必须经过最长传播时间的PWM控制信号的最大延迟时间，然后将该PWM控制信号的延迟设定为基本为零的延迟来实现。 此后，可以通过从最长传播时间减去每个其它PWM控制信号的传播时间来确定其它PWM控制信号的所有其他延迟时间设置。 从而确保所有的PWM控制信号到达它们各自的功率晶体管控制节点时具有与其离开它们各自的PWM发生器时基本相同的时间关系。

公开(公告)号：US20240413751A1

公开(公告)日：2024-12-12

申请号：US18737148

申请日：2024-06-07

Applicant: Microchip Technology Incorporated

Inventor： Yong Yuenyongsgool ,  Andreas Reiter ,  Stephen Bowling

IPC: H02M3/158

Abstract: A device includes a switched power converter with an inductor, the power converter to produce a voltage output based on a pulse-width modulated (PWM) signal, and produce a peak current feedback signal, the peak current feedback signal representative of a peak current through the inductor. The device includes a comparator to generate a PWM control input (PCI) signal based on whether the peak current feedback signal has reached a reference current. The device includes a PWM generation circuit to generate the PWM signal to control switching of the switched power converter based on the PCI signal. The device includes a synchronization circuit to delay a change in the PCI signal.