公开(公告)号：US09589644B2

公开(公告)日：2017-03-07

申请号：US13647179

申请日：2012-10-08

Applicant: Micron Technology, Inc.

Inventor： Aaron Yip

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24

Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

Abstract translation: 公开了一种装置和方法，例如包括在编程操作的第一部分期间将存储器单元块的未选择子块中的存储器单元串的通道材料预充电到预充电电压的方法。 然后可以在编程操作的第二部分期间将编程电压施加到存储器单元块的选定子块中的选定存储单元。 所选择的存储器单元被耦合到与未选择的子块中的未选择的存储单元相同的访问线。 公开了附加的方法和装置。

公开(公告)号：US09099189B2

公开(公告)日：2015-08-04

申请号：US14039796

申请日：2013-09-27

Applicant: Micron Technology, Inc.

Inventor： Aaron Yip

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

Abstract: Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage, and selectively discharging the one data line depending upon a data value of a selected memory cell of a string of memory cells associated with the one data line.

Abstract translation: 操作存储器件的方法，包括将相邻数据线对预充电到特定电压，将相邻数据线对的一条数据线与特定电压隔离，同时将相邻数据线对的另一条数据线保持在特定电压 并且根据与该一条数据线相关联的一组存储单元的所选存储单元的数据值选择性地放电一条数据线。

公开(公告)号：US20140098606A1

公开(公告)日：2014-04-10

申请号：US13647179

申请日：2012-10-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron Yip

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24

Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

Abstract translation: 公开了一种装置和方法，例如包括在编程操作的第一部分期间将存储器单元块的未选择子块中的存储器单元串的通道材料预充电到预充电电压的方法。 然后可以在编程操作的第二部分期间将编程电压施加到存储器单元块的选定子块中的选定存储单元。 所选择的存储器单元被耦合到与未选择的子块中的未选择的存储单元相同的访问线。 公开了附加的方法和装置。

公开(公告)号：US12125786B2

公开(公告)日：2024-10-22

申请号：US17819004

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/00 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B43/50 ,  H10B41/00 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US11670370B2

公开(公告)日：2023-06-06

申请号：US17514899

申请日：2021-10-29

Applicant: Micron Technology, Inc.

Inventor： Aaron Yip

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/14 ,  G11C16/08 ,  H01L27/11575

CPC classification number: G11C16/0483 ,  G11C16/0458 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C2216/02 ,  H01L27/11575 ,  H01L27/11582

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

公开(公告)号：US11605588B2

公开(公告)日：2023-03-14

申请号：US16723758

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Paolo Tessariol ,  Aaron Yip ,  Naveen Kaushik

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first pillar of a first memory cell string; a second pillar of a second memory cell string; a first conductive structure extending in a first direction, the first conductive structure located over and in electrical contact with the first pillar; a second conductive structure extending in the first direction, the second conductive structure located over and in electrical contact with the second pillar; a select gate coupled to the first and second memory cell strings; a first data line located on a first level of the apparatus and extending in a second direction, the first data line located over the first conductive structure and in electrical contact with the first conductive structure; and a second data line located on a second level of the apparatus and extending in the second direction, the second data line located over the second conductive structure and in electrical contact with the second conductive structure.

公开(公告)号：US20220384341A1

公开(公告)日：2022-12-01

申请号：US17819004

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11575

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US20210005262A1

公开(公告)日：2021-01-07

申请号：US16995361

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Aaron Yip

IPC: G11C16/10 ,  H01L27/11529 ,  H01L27/11573

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

公开(公告)号：US10409506B2

公开(公告)日：2019-09-10

申请号：US16117348

申请日：2018-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F12/0804 ,  G06F13/28 ,  G06F12/0846

Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.

公开(公告)号：US20190147954A1

公开(公告)日：2019-05-16

申请号：US16228534

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Aaron Yip

IPC: G11C16/04 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.