公开(公告)号：US10903218B2

公开(公告)日：2021-01-26

申请号：US16909770

申请日：2020-06-23

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy ,  Ashonita A. Chavan

IPC: H01L27/11509 ,  H01L27/11507 ,  H01L27/11504 ,  H01G4/06 ,  H01L49/02 ,  H01G4/40 ,  G11C11/22 ,  H01G4/008

Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10707220B2

公开(公告)日：2020-07-07

申请号：US15691806

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Ashonita A. Chavan ,  Alessandro Calderoni ,  D. V. Nirmal Ramaswamy

IPC: H01L27/11507 ,  H01L27/108 ,  H01L29/423 ,  H01L49/02

Abstract: Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a substrate and a ferroelectric capacitor formed on the BRAD.

公开(公告)号：US20200090728A1

公开(公告)日：2020-03-19

申请号：US16586334

申请日：2019-09-27

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy ,  Kirk Prall ,  Ferdinando Bedeschi

IPC: G11C11/22 ,  G11C29/52 ,  G06F11/10

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

公开(公告)号：US20190074060A1

公开(公告)日：2019-03-07

申请号：US16176417

申请日：2018-10-31

Applicant: Micron Technology, Inc.

Inventor： Emiliano Faraoni ,  Scott E. Sills ,  Alessandro Calderoni ,  Adam Johnson

IPC: G11C13/00

Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.

公开(公告)号：US20180342294A1

公开(公告)日：2018-11-29

申请号：US16057170

申请日：2018-08-07

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

公开(公告)号：US10141040B2

公开(公告)日：2018-11-27

申请号：US15693032

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/22

Abstract: Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.

公开(公告)号：US20180331283A1

公开(公告)日：2018-11-15

申请号：US16041374

申请日：2018-07-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni

IPC: H01L45/00 ,  H01L27/11507 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/11507 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06

Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.

公开(公告)号：US10083732B2

公开(公告)日：2018-09-25

申请号：US15645106

申请日：2017-07-10

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy ,  Kirk Prall ,  Ferdinando Bedeschi

IPC: G11C11/22 ,  G11C29/52 ,  G06F11/10

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

公开(公告)号：US20180137908A1

公开(公告)日：2018-05-17

申请号：US15858831

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Bei Wang ,  Alessandro Calderoni ,  Wayne Kinney ,  Adam Johnson ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/22 ,  G11C11/56 ,  G11C14/00

CPC classification number: G11C11/2275 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/5657 ,  G11C14/00 ,  H01L27/11502 ,  H01L27/11507

Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

公开(公告)号：US20140169066A1

公开(公告)日：2014-06-19

申请号：US13921951

申请日：2013-06-19

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

Abstract translation: 本公开包括用于感测电阻式存储单元的装置和方法。 许多实施例包括对存储器单元执行感测操作以确定与存储器单元相关联的当前值，将编程信号施加到存储器单元，以及基于与存储器单元相关联的当前值来确定存储器单元的数据状态 在施加编程信号之前应用编程信号的存储单元和与存储器单元相关联的当前值。