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    Sensing techniques for a memory cell
    21.
    发明授权
    Sensing techniques for a memory cell 有权

    公开(公告)号：US10916288B1

    公开(公告)日：2021-02-09

    申请号：US16515666

    申请日：2019-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo ,  Efrem Bolandrina ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

    IPC: G11C7/00 ,  G11C11/22

    Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.

    SENSING TECHNIQUES FOR A MEMORY CELL
    22.
    发明申请
    SENSING TECHNIQUES FOR A MEMORY CELL 有权

    公开(公告)号：US20210020221A1

    公开(公告)日：2021-01-21

    申请号：US16515666

    申请日：2019-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo ,  Efrem Bolandrina ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

    IPC: G11C11/22

    Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.

    Reference voltage management
    23.
    发明授权
    Reference voltage management 有权

    公开(公告)号：US10692557B1

    公开(公告)日：2020-06-23

    申请号：US16381702

    申请日：2019-04-11

    Applicant: Micron Technology, Inc.

    Inventor： Efrem Bolandrina ,  Ferdinando Bedeschi

    IPC: G11C11/22

    Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.

    MEMORY DEVICE WITH REDUCED NEIGHBOR MEMORY CELL DISTURBANCE
    24.
    发明申请
    MEMORY DEVICE WITH REDUCED NEIGHBOR MEMORY CELL DISTURBANCE 审中-公开

    公开(公告)号：US20190013072A1

    公开(公告)日：2019-01-10

    申请号：US16109066

    申请日：2018-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Efrem Bolandrina ,  Daniele Vimercati

    IPC: G11C13/00 ,  G11C11/16

    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.

    Shared decoder architecture for three-dimensional memory arrays
    26.
    发明授权
    Shared decoder architecture for three-dimensional memory arrays 有权

    公开(公告)号：US12260907B2

    公开(公告)日：2025-03-25

    申请号：US18622033

    申请日：2024-03-29

    Applicant: Micron Technology, Inc.

    Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Efrem Bolandrina ,  Ferdinando Bedeschi

    IPC: G11C13/04 ,  G11C13/00

    Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

    Techniques for indicating row activation
    29.
    发明授权
    Techniques for indicating row activation 有权

    公开(公告)号：US11887688B2

    公开(公告)日：2024-01-30

    申请号：US17511314

    申请日：2021-10-26

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Efrem Bolandrina

    IPC: G11C7/10 ,  G11C8/18

    CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1048 ,  G11C8/18

    Abstract: Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.

    Reference voltage management
    30.
    发明授权
    Reference voltage management 有权

    公开(公告)号：US11810609B2

    公开(公告)日：2023-11-07

    申请号：US17563395

    申请日：2021-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Efrem Bolandrina ,  Ferdinando Bedeschi

    IPC: G11C11/00 ,  G11C11/22

    CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2255 ,  G11C11/2257

    Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.

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