公开(公告)号：US11024367B2

公开(公告)日：2021-06-01

申请号：US17017545

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/406 ,  G11C7/18 ,  H01L25/10 ,  G11C11/4096

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

公开(公告)号：US10964375B2

公开(公告)日：2021-03-30

申请号：US16375716

申请日：2019-04-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C11/408

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. A memory device may include a number of memory banks, at least some of which may be simultaneously entered into a refresh mode. A given memory bank may perform an auto-refresh operation or a targeted refresh operation, which may draw less power than the auto-refresh operation. The timing of the targeted refresh operations may be staggered between the refreshing memory banks, such that a portion of the refreshing memory banks are performing a targeted refresh operation simultaneously with a portion of the refreshing memory banks performing an auto-refresh operation.

公开(公告)号：US10910033B2

公开(公告)日：2021-02-02

申请号：US16220742

申请日：2018-12-14

Applicant: Micron Technology, Inc.

Inventor： Stephen Michael Kaminski ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Dale Herber Hiscock ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4091

Abstract: Methods, systems, and devices for refresh-related activation in memory are described. A memory device may conduct a refresh operation to preserve the integrity of data. A refresh operation may be associated with a refresh time where the memory device is unable to execute or issue any commands (e.g., access commands). By posting (e.g., saving) one or more commands and/or row addresses during the refresh time, the memory device may be configured to execute the saved commands and/or re-open one or more rows associated with the saved row addresses at a later time (e.g., upon completion of the refresh operation). Accordingly, fewer commands may be issued to activate the memory cells after the refresh time.

公开(公告)号：US20200227113A1

公开(公告)日：2020-07-16

申请号：US16247277

申请日：2019-01-14

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Debra M. Bell ,  George B. Raad ,  Brian P. Callaway ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/403 ,  G11C11/408

Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.

公开(公告)号：US10692562B2

公开(公告)日：2020-06-23

申请号：US16734241

申请日：2020-01-03

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/16 ,  G11C11/00 ,  G11C11/22 ,  G11C13/00

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

公开(公告)号：US20200176047A1

公开(公告)日：2020-06-04

申请号：US16205980

申请日：2018-11-30

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  Sang-Kyun Park ,  Makoto Kitayama

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/22

Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.

公开(公告)号：US20190371392A1

公开(公告)日：2019-12-05

申请号：US16543477

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C11/406

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

公开(公告)号：US12197264B2

公开(公告)日：2025-01-14

申请号：US17094579

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Gary L. Howe ,  Miles S. Wiscombe ,  Eric J. Stave

IPC: G06F1/32 ,  G06F1/3203 ,  G11C11/40 ,  G11C11/4074

Abstract: Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.

公开(公告)号：US20240233791A1

公开(公告)日：2024-07-11

申请号：US18615399

申请日：2024-03-25

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Lawrence D. Smith ,  James S. Rehmeyer

IPC: G11C7/22 ,  G11C7/10 ,  G11C17/16

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/109 ,  G11C17/16

Abstract: Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

公开(公告)号：US11930636B2

公开(公告)日：2024-03-12

申请号：US17468523

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Toshihiko Miyashita

IPC: H10B20/20 ,  G11C17/16 ,  G11C17/18

CPC classification number: H10B20/20 ,  G11C17/16 ,  G11C17/18

Abstract: Transistor antifuses are disclosed. An apparatus may include an antifuse that may be configurable either as a short between a first node and a second node or as an open between the first node and the second node. The antifuse may include a selection transistor and an antifuse transistor. A source or drain of the selection transistor may be electrically coupled to the first node. A gate of the selection transistor may be configured to receive a selection voltage. A gate of the antifuse transistor may be electrically coupled the other of the source or drain of the selection transistor. A source or drain of the antifuse transistor may be electrically coupled to the second node. Associated devices, systems, and methods are also disclosed.