公开(公告)号：US11335775B2

公开(公告)日：2022-05-17

申请号：US16952774

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Jaydip Guha ,  Scott E. Sills ,  Yi Fang Lee

IPC: H01L29/10 ,  H01L27/06 ,  H01L27/108 ,  H01L29/24 ,  H01L21/8234 ,  H01L27/11502

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11088147B2

公开(公告)日：2021-08-10

申请号：US16453788

申请日：2019-06-26

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Saurabh Keshav ,  Srinivas Pulugurtha ,  Mohd Kamran Akhtar ,  James B. Franek ,  Alex J. Schrinsky

IPC: H01L27/108 ,  H01L21/263 ,  H01L21/223

Abstract: Apparatus, such as electronic devices and structures thereof, include at least one doped surface of a base (e.g., semiconductor) material. A dopant of the at least one doped surface is concentrated along the surface, defining a thickness, on or in the base material, not exceeding about one atomic layer. Methods for forming the doped surfaces involve gas-phase doping exposed surfaces of the base material in situ, within a same material-removal tool used to form at least one opening defined at least partially by the base material and into which the dopant is to be introduced.

公开(公告)号：US10147727B2

公开(公告)日：2018-12-04

申请号：US15895587

申请日：2018-02-13

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami ,  Zailong Bian ,  Yushi Hu ,  Eric R. Blomiley ,  Jaydip Guha ,  Thomas Gehrke

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/08 ,  H01L29/49 ,  H01L23/532 ,  H01L23/528

Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.

公开(公告)号：US20180175039A1

公开(公告)日：2018-06-21

申请号：US15895587

申请日：2018-02-13

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami ,  Zailong Bian ,  Yushi Hu ,  Eric R. Blomiley ,  Jaydip Guha ,  Thomas Gehrke

IPC: H01L27/108 ,  H01L29/423 ,  H01L23/532 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L27/10823 ,  H01L23/5283 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966

Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.

公开(公告)号：US20180138182A1

公开(公告)日：2018-05-17

申请号：US15349808

申请日：2016-11-11

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami ,  Zailong Bian ,  Yushi Hu ,  Eric R. Blomiley ,  Jaydip Guha ,  Thomas Gehrke

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/08 ,  H01L29/49 ,  H01L23/532

CPC classification number: H01L27/10823 ,  H01L23/5283 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966

Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.

公开(公告)号：US09972628B1

公开(公告)日：2018-05-15

申请号：US15349808

申请日：2016-11-11

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami ,  Zailong Bian ,  Yushi Hu ,  Eric R. Blomiley ,  Jaydip Guha ,  Thomas Gehrke

IPC: H01L29/49 ,  H01L27/108 ,  H01L29/423 ,  H01L29/08 ,  H01L23/532

CPC classification number: H01L27/10823 ,  H01L23/5283 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966

Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.

公开(公告)号：US20150249089A1

公开(公告)日：2015-09-03

申请号：US14712291

申请日：2015-05-14

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Suraj J. Mathew ,  Jaydip Guha

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/02

CPC classification number: H01L27/10832 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/28525 ,  H01L27/10861 ,  H01L27/10873 ,  H01L29/945

Abstract: A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed.

Abstract translation: 存储单元包括晶体管器件，其包括一对源极/漏极，包括沟道的主体以及可操作地邻近沟道的栅极结构。 存储单元包括电容器，该电容器包括一对在其间具有电容器电介质的电容器电极。 电容器电极之一是通道或电耦合到通道。 电容器电极中的另一个包括主体而不是通道的一部分。 还公开了方法。

公开(公告)号：US09054216B2

公开(公告)日：2015-06-09

申请号：US14319201

申请日：2014-06-30

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/66 ,  H01L29/417 ,  H01L27/11

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

公开(公告)号：US20250126773A1

公开(公告)日：2025-04-17

申请号：US18999244

申请日：2024-12-23

Applicant: Micron Technology, Inc.

Inventor： Anthony J. Kanago ,  Jaydip Guha ,  Srinivas Pulugurtha ,  Soichi Sugiura

IPC: H10B12/00 ,  G11C11/4096 ,  G11C29/54 ,  H10D30/67

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.

公开(公告)号：US11929411B2

公开(公告)日：2024-03-12

申请号：US17411643

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Sau Ha Cheung ,  Soichi Sugiura ,  Jaydip Guha ,  Anthony Kanago ,  Richard Beeler

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/51 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/512 ,  H10B12/053 ,  H10B12/34

Abstract: A method of forming a recessed access device comprises forming a trench in semiconductor material. Sidewalls and a bottom of the trench are lined with low-k gate-insulator material. The low-k gate-insulator material is characterized by its dielectric constant k being no greater than 4.0. Sacrificial material is formed in a bottom portion of the trench over the low-k gate-insulator material and over the trench bottom. A high-k gate-insulator material is formed in an upper portion of the trench above the sacrificial material and laterally-inward of the low-k gate-insulator material that is in the upper portion of the trench. The high-k gate-insulator material is characterized by its dielectric constant k being greater than 4.0. The sacrificial material is replaced with a conductive gate that has its top above a bottom of the high-k gate-insulator material. A pair of source/drain regions is formed in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions and extends along the trench sidewalls and around the trench bottom. Other embodiments, including structure independent of method, are disclosed.