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公开(公告)号：US20240395338A1
公开(公告)日：2024-11-28
申请号：US18790480
申请日：2024-07-31
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Violante Moschiano , Jeffrey S. McNeil , James Fitzpatrick , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Patrick R. Khayat
Abstract: Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.
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公开(公告)号：US12141437B2
公开(公告)日：2024-11-12
申请号：US17974799
申请日：2022-10-27
Applicant: Micron Technology, Inc.
Inventor： Jeremy Binfet , Violante Moschiano , James Fitzpatrick , Kishore Kumar Muccherla , Jeffrey S. McNeil , Phong Sy Nguyen
IPC: G06F3/06
Abstract: A memory device comprising an array of memory cells organized into a set of sub-blocks and a set of wordlines. Control logic is operatively coupled with the array of memory cells, the control logic to perform operations including: receiving a program command from a processing device, the program command including information indicative of a physical address associated with a retired wordline of the set of wordlines; in response to detecting the information within the program command, generating dummy data that is one of pseudo-random data, all one values, or all zero values; and causing the dummy data to be programmed to memory cells of multiple sub-blocks of the set of sub-blocks that are selectively connected to the retired wordline.
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公开(公告)号：US12131028B2
公开(公告)日：2024-10-29
申请号：US18121494
申请日：2023-03-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jeffrey S. McNeil , Jonathan S. Parry , Ugo Russo , Akira Goda , Kishore Kumar Muchherla , Violante Moschiano , Niccolo' Righetti , Silvia Beltrami
CPC classification number: G06F3/0611 , G06F3/0659 , G06F3/0679
Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.
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公开(公告)号：US11861233B2
公开(公告)日：2024-01-02
申请号：US17691467
申请日：2022-03-10
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil , Kishore Kumar Muchherla , Sivagnanam Parthasarathy , Patrick R. Khayat , Sundararajan Sankaranarayanan , Jeremy Binfet , Akira Goda
CPC classification number: G06F3/0659 , G06F3/0619 , G06F3/0673 , G11C16/26 , G11C16/0483
Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.
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公开(公告)号：US20230386533A1
公开(公告)日：2023-11-30
申请号：US18232949
申请日：2023-08-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Eric N. Lee , Kishore Kumar Muchherla , Jeffrey S. McNeil , Jung-Sheng Hoei
CPC classification number: G11C7/106 , G11C7/1057 , G11C7/222 , G11C7/1087 , G11C7/14 , G11C7/1084
Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.
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Patent Agency Ranking
公开(公告)号：US20230195385A1
公开(公告)日：2023-06-22
申请号：US17691467
申请日：2022-03-10
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil , Kishore Kumar Muchherla , Sivagnanam Parthasarathy , Patrick Khayat , Sundararajan Sankaranarayanan , Jeremy Binfet , Akira Goda
CPC classification number: G06F3/0659 , G11C16/26 , G06F3/0619 , G06F3/0673 , G11C16/0483
Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.
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公开(公告)号：US11605434B1
公开(公告)日：2023-03-14
申请号：US17462305
申请日：2021-08-31
Applicant: Micron Technology, Inc.
Inventor： Jonathan S. Parry , Jeffrey S. McNeil , Giuseppe Cariello , Kishore Kumar Muchherla , Reshmi Basu
Abstract: Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.
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公开(公告)号：US20230068702A1
公开(公告)日：2023-03-02
申请号：US17591406
申请日：2022-02-02
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Violante Moschiano , Akira Goda , Jeffrey S. McNeil , Jung Sheng Hoei , Sivagnanam Parthasarathy , James Fitzpatrick , Patrick R. Khayat
IPC: G06F3/06
Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.
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公开(公告)号：US20220359025A1
公开(公告)日：2022-11-10
申请号：US17873716
申请日：2022-07-26
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil , Jason Lee Nevill , Tommaso Vali
Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.
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公开(公告)号：US11417406B2
公开(公告)日：2022-08-16
申请号：US16907594
申请日：2020-06-22
Applicant: Micron Technology, Inc.
Inventor： Jeffrey S. McNeil , Jason Lee Nevill , Tommaso Vali
Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.
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