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    Time-based access of a memory cell
    21.
    发明授权
    Time-based access of a memory cell 有权

    公开(公告)号：US10755760B2

    公开(公告)日：2020-08-25

    申请号：US16512982

    申请日：2019-07-16

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo

    IPC: G11C11/22 ,  G11C11/00 ,  G11C11/56

    Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

    Techniques for read operations
    22.
    发明授权
    Techniques for read operations 有权

    公开(公告)号：US10726917B1

    公开(公告)日：2020-07-28

    申请号：US16254962

    申请日：2019-01-23

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

    IPC: G11C13/00 ,  G11C16/04 ,  G11C7/10 ,  G11C16/28

    Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

    TECHNIQUES FOR READ OPERATIONS
    23.
    发明申请
    TECHNIQUES FOR READ OPERATIONS 审中-公开

    公开(公告)号：US20200234761A1

    公开(公告)日：2020-07-23

    申请号：US16254962

    申请日：2019-01-23

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

    IPC: G11C13/00 ,  G11C16/04 ,  G11C16/28 ,  G11C7/10

    Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

    Self-boost, source following, and sample-and-hold for accessing memory cells
    24.
    发明授权
    Self-boost, source following, and sample-and-hold for accessing memory cells 有权

    公开(公告)号：US10475498B2

    公开(公告)日：2019-11-12

    申请号：US15653276

    申请日：2017-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

    IPC: G11C11/22 ,  G11C11/404 ,  G11C11/409 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/06 ,  G11C27/02

    Abstract: Methods, systems, and devices for operating a memory cell or cells are described. A capacitor coupled with an access line may be precharged and then boosted such that the charge stored in the capacitor is elevated to a higher voltage with respect to a memory cell. The boosted charge in the capacitor may support sensing operations that would otherwise require a relatively higher voltage. Some embodiments may employ charge amplification between an access line and a sense component, which may amplify signals between the memory cell and the sense component, and reduce charge sharing between these components. Some embodiments may employ “sample-and-hold” operations, which may re-use certain components of a sense component to separately generate a signal and a reference, reducing sensitivity to manufacturing and/or operational tolerances. In some embodiments, sensing may be further improved by employing “self-reference” operations that use a memory cell to generate its own reference.

    Variable filter capacitance
    25.
    发明授权
    Variable filter capacitance 有权

    公开(公告)号：US10475489B2

    公开(公告)日：2019-11-12

    申请号：US16020834

    申请日：2018-06-27

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

    IPC: G11C7/14 ,  G11C11/22 ,  G11C11/24 ,  G11C11/408 ,  G11C5/06 ,  G11C8/08 ,  G11C8/14 ,  G11C5/14

    Abstract: Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.

    Compensating for variations in selector threshold voltages
    28.
    发明授权
    Compensating for variations in selector threshold voltages 有权

    公开(公告)号：US09966127B2

    公开(公告)日：2018-05-08

    申请号：US15291711

    申请日：2016-10-12

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

    IPC: G11C11/22

    CPC classification number: G11C11/2259 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/2293

    Abstract: Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing operation once the selection component is activated. The first voltage may be applied during a first portion of an access operation and may be used in determining a threshold voltage of the selection component. The subsequently applied second voltage may be applied during a second portion of the access operation and may have a magnitude associated with a preferred voltage for accessing a ferroelectric capacitor of the memory cell. In some cases, the second voltage has a greater rate of increase over time (e.g., a greater “ramp”) than the first voltage.

    GROUND REFERENCE SCHEME FOR A MEMORY CELL
    29.
    发明申请
    GROUND REFERENCE SCHEME FOR A MEMORY CELL 有权

    公开(公告)号：US20170256300A1

    公开(公告)日：2017-09-07

    申请号：US15057914

    申请日：2016-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

    IPC: G11C11/22

    CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2293

    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

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