公开(公告)号：US10103164B2

公开(公告)日：2018-10-16

申请号：US15290227

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11575

Abstract: A 3D semiconductor device is provided, including several memory layers vertically stacked on a substrate, an upper selection layer formed on the memory layers, a lower selection layer formed above the substrate, several strings formed vertically to the memory layers and the substrate, several bit lines parallel to each other and disposed above the substrate. The memory layers are parallel to each other, and the strings are electrically connected to the upper selection layer and the lower selection layer. The bit lines are positioned under the memory layers.

公开(公告)号：US10090232B1

公开(公告)日：2018-10-02

申请号：US15810256

申请日：2017-11-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/528

Abstract: A bumpless fan-out chip stacking structure includes a first die disposed on the substrate, a first dielectric layer conformally covering on the first die, a first RDL disposed on the first dielectric layer, a first via plug electrically connecting the first die to the first RDL, a first capping layer conformally covering on the first RDL, a second die attached on the first capping layer, a second dielectric layer conformally covering on the second die, a second RDL disposed on the second dielectric layer, a second via plug electrically connecting the second die to the second RDL, a second capping layer conformally covering on the second RDL, a patterned conductive layer disposed on the second capping layer and an interlayer connection structure electrically connecting the patterned conductive layer to the first RDL and the second RDL respectively.

公开(公告)号：US10026692B2

公开(公告)日：2018-07-17

申请号：US15096315

申请日：2016-04-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a stack structure, an etching stop layer, and a conductive structure. The stack structure includes a plurality of conductive layers and a plurality of insulating layers stacked interlacedly. The etching stop layer is formed on a sidewall of the stack structure. An energy gap of the etching stop layer is larger than 6 eV. The conductive structure is electrically connected to at least one of the conductive layers.

公开(公告)号：US09812176B2

公开(公告)日：2017-11-07

申请号：US15364291

申请日：2016-11-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: G11C5/02 ,  G11C16/10 ,  G11C5/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C16/10 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer≧2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=⅕ to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines. M array regions of the N array regions are configured to operate simultaneously. M is an integer. M/N=½ or 1.

公开(公告)号：US09502349B2

公开(公告)日：2016-11-22

申请号：US14640869

申请日：2015-03-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/115 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into separate word lines, each defining a block of memory cells. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. String select lines run above the conductive layers, each intersection of a pillar and an string select line defining a respective select gate of the pillar. Bit lines run above the SSLs. Ground select lines run below the conductive layers, each intersection of a pillar and a ground select line defining a respective ground select gate of the pillar. The ground select lines are divided laterally such that the number of ground select lines in each block is greater than 1 but less than the number of string select lines in the block.

Abstract translation: 大体描述的是，存储器件具有多层导电层，它们横向划分成单独的字线，每个限定一个存储单元块。 垂直取向的支柱各自包括在支柱和导电层之间的交叉点处的串联存储单元。 在导电层之上运行的串选择线，柱的每个交叉点和定义柱的相应选择门的串选择线。 位线在SSL之上运行。 接地选择线在导电层下方延伸，柱子和接地选择线的每个交叉点定义了柱的相应的地选择门。 接地选择线横向划分，使得每个块中的接地选择线的数量大于1但小于块中的字符串选择线的数量。

公开(公告)号：US20160284668A1

公开(公告)日：2016-09-29

申请号：US14669015

申请日：2015-03-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/04105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01074

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure comprises a substrate, a first chip, a first dielectric layer, a dielectric encapsulation layer and at least one first via. The first chip is disposed on the substrate. The first chip has a first landing area. The first dielectric layer is disposed on the first chip. The dielectric encapsulation layer encapsulates the first chip and the first dielectric layer. The at least one first via penetrates through the dielectric encapsulation layer and the first dielectric layer. The at least one first via connects to the first landing area of the first chip.

Abstract translation: 提供半导体封装结构及其制造方法。 半导体封装结构包括衬底，第一芯片，第一介电层，电介质封装层和至少一个第一通孔。 第一芯片设置在基板上。 第一个芯片有第一个着陆区域。 第一介电层设置在第一芯片上。 电介质封装层封装第一芯片和第一介电层。 至少一个第一通孔穿过电介质封装层和第一介电层。 所述至少一个第一通孔连接到第一芯片的第一着陆区域。

公开(公告)号：US09437605B2

公开(公告)日：2016-09-06

申请号：US14857651

申请日：2015-09-17

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L27/115 ,  H01L27/02

CPC classification number: H01L27/1157 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/11582

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into word lines. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the layers. String select lines run above the conductive layers and define select gates of the pillars. Bit lines run above the SSLs. The pillars are arranged on a regular grid having a unit cell area α, and adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (α/pBL). Ground select lines run below the conductive layers and define ground select gates of the pillars. The ground select lines, too, may have respective widths in the bit line direction which are at least as large as (α/pBL).

Abstract translation: 大致描述，存储器件具有横向划分成字线的多层导电层。 垂直取向的柱子各自包括在柱和层之间的交叉点处的串联存储器单元。 字符串选择线在导电层之上运行，并定义柱的选择栅。 位线在SSL之上运行。 支柱布置在具有单元单元面积α的规则网格上，并且相邻的串选择线具有至少与（α/ pBL）一样大的位线方向上的相应宽度。 接地选择线在导电层下方延伸并定义支柱的接地选择门。 接地选择线也可以具有至少与（α/ pBL）一样大的位线方向上的相应宽度。

公开(公告)号：US09425191B2

公开(公告)日：2016-08-23

申请号：US13965269

申请日：2013-08-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Yen-Hao Shih ,  Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L27/06 ,  H01L27/115

CPC classification number: H01L27/0688 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.

Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括衬底，3D存储器阵列，外围电路和导电连接结构。 3D存储器阵列和外围电路堆叠在基板上。 外围电路包括图案化金属层和电连接到图案化金属层的接触结构。 导电连接结构电连接到图案化的金属层。 3D存储器阵列经由导电连接结构电连接到外围电路。

公开(公告)号：US20160240254A1

公开(公告)日：2016-08-18

申请号：US14623963

申请日：2015-02-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: G11C16/08

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A memory device includes a plurality of stacks of conductive strips, a plurality of conductive vertical structures arranged orthogonally to the plurality of stacks, memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of conductive vertical structures, multiples pluralities of conductive lines, and control circuitry. The plurality of stacks of conductive strips alternate with insulating strips, including at least a bottom layer of conductive strips, a plurality of intermediate layers of conductive strips, and a top layer of conductive strips. A first plurality of conductive lines electrically couple to the top layer of the conductive strips. A second plurality of conductive lines and a third plurality of conductive lines electrically couple to the plurality of intermediate layers. The control circuitry causes the first plurality of conductive lines to select at least a first particular stack in the plurality of stacks, the second plurality of conductive lines to select at least the first particular stack in the plurality of stacks, and the third plurality of conductive lines to select at least one particular layer in the plurality of intermediate layers.

Abstract translation: 存储器件包括多个导电条的叠层，与多个堆叠正交布置的多个导电垂直结构，在多个堆叠的侧表面之间的交叉点处的界面区域中的存储元件和多个导电垂直结构 ，多个导线和多个控制电路。 导电条的多个叠层与绝缘条交替，包括至少底层的导电条，多个导电条的中间层和导电条的顶层。 第一多个导电线电耦合到导电条的顶层。 电耦合到多个中间层的第二多个导电线和第三多个导电线。 所述控制电路使得所述第一多个导线选择所述多个堆叠中的至少第一特定堆叠，所述第二多个导电线至少选择所述多个堆叠中的所述第一特定堆叠，以及所述第三多个导电 行以选择多个中间层中的至少一个特定层。

公开(公告)号：US09373632B2

公开(公告)日：2016-06-21

申请号：US14582963

申请日：2014-12-24

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L27/115 ,  H01L27/02

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. SSLs run above the conductive layers, each intersection of a pillar and an SSL defining a respective select gate of the pillar. Bit lines run above the SSLs. The pillars are arranged on a regular grid which is rotated relative to the bit lines. The grid may have a square, rectangle or diamond-shaped unit cell, and may be rotated relative to the bit lines by an angle θ where tan(θ)=±X/Y, where X and Y are co-prime integers. The SSLs may be made wide enough so as to intersect two pillars on one side of the unit cell, or all pillars of the cell, or sufficiently wide as to intersect pillars in two or more non-adjacent cells.

Abstract translation: 大体描述，存储器件具有多层导电层。 垂直取向的支柱各自包括在支柱和导电层之间的交叉点处的串联存储单元。 SSL在导电层之上运行，柱和SSL的每个交叉点定义了柱的相应选择门。 位线在SSL之上运行。 柱子布置在相对于位线旋转的规则格栅上。 栅格可以具有正方形，矩形或菱形单元，并且可以相对于位线旋转角度＆amp; 其中tan（＆thetas;）=±X / Y，其中X和Y是co-prime整数。 SSL可以制得足够宽，以便在单元电池的一侧或电池的所有支柱上交叉两个柱，或者足够宽以便在两个或更多个非相邻电池中与柱相交。