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    Semiconductor integrated circuit device for real-time processing
    21.
    发明授权
    Semiconductor integrated circuit device for real-time processing 有权
    半导体集成电路器件实时处理

    公开(公告)号：US07529874B2

    公开(公告)日：2009-05-05

    申请号：US11545510

    申请日：2006-10-11

    申请人： Makoto Saen ,  Tetsuya Yamada ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

    发明人： Makoto Saen ,  Tetsuya Yamada ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

    IPC分类号： G06F13/00 ,  G06F9/00

    CPC分类号： G06F9/4818 ,  G06F9/485

    摘要： A technology capable of efficiently performing the processes by using limited resources in an LSI where a plurality of real-time applications are parallelly processed is provided. To provide such a technology, a mechanism is provided in which a plurality of processes to be executed on a plurality of processing units in an LSI are managed throughout the LSI in a unified manner. For each process to be managed, a priority is calculated based on the state of progress of the process, and the execution of the process is controlled according to the priority. A resource management unit IRM or program that collects information such as a process state from each of the processing units executing the processes and calculates a priority for each process is provided. Also, a programmable interconnect unit and storage means for controlling a process execution sequence according to the priority are provided.

    摘要翻译： 提供一种能够通过在多个实时应用并行处理的LSI中使用有限资源来有效地执行处理的技术。 为了提供这样的技术，提供了一种机制，其中在LSI中的多个处理单元上执行的多个处理以统一的方式在整个LSI中被管理。 对于要管理的每个进程，根据进程的进度来计算优先级，根据优先级来控制进程的执行。 提供了从执行处理的每个处理单元收集诸如处理状态的信息的资源管理单元IRM或程序，并且计算每个处理的优先级。 另外，提供了一种用于根据优先级控制处理执行顺序的可编程互连单元和存储装置。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR REAL-TIME PROCESSING
    22.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR REAL-TIME PROCESSING 有权
    用于实时处理的半导体集成电路设备

    公开(公告)号：US20090089786A1

    公开(公告)日：2009-04-02

    申请号：US11545510

    申请日：2006-10-11

    申请人： Makoto Saen ,  Tetsuya Yamada ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

    发明人： Makoto Saen ,  Tetsuya Yamada ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4818 ,  G06F9/485

    摘要： A technology capable of efficiently performing the processes by using limited resources in an LSI where a plurality of real-time applications are parallelly processed is provided. To provide such a technology, a mechanism is provided in which a plurality of processes to be executed on a plurality of processing units in an LSI are managed throughout the LSI in a unified manner. For each process to be managed, a priority is calculated based on the state of progress of the process, and the execution of the process is controlled according to the priority. A resource management unit IRM or program that collects information such as a process state from each of the processing units executing the processes and calculates a priority for each process is provided. Also, a programmable interconnect unit and storage means for controlling a process execution sequence according to the priority are provided.

    摘要翻译： 提供一种能够通过在多个实时应用并行处理的LSI中使用有限资源来有效地执行处理的技术。 为了提供这样的技术，提供了一种机制，其中在LSI中的多个处理单元上执行的多个处理以统一的方式在整个LSI中被管理。 对于要管理的每个进程，根据进程的进度来计算优先级，根据优先级来控制进程的执行。 提供了从执行处理的每个处理单元收集诸如处理状态的信息的资源管理单元IRM或程序，并且计算每个处理的优先级。 另外，提供了一种用于根据优先级控制处理执行顺序的可编程互连单元和存储装置。

    SEMICONDUCTOR DEVICE
    25.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20100078635A1

    公开(公告)日：2010-04-01

    申请号：US12465819

    申请日：2009-05-14

    申请人： Yuki Kuroda ,  Makoto Saen ,  Hiroyuki Mizuno ,  Kiyoto Ito

    发明人： Yuki Kuroda ,  Makoto Saen ,  Hiroyuki Mizuno ,  Kiyoto Ito

    IPC分类号： H01L23/58 ,  H01L21/50

    CPC分类号： H01L25/18 ,  G11C5/02 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00014

    摘要： As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path. Further, an interposer for facilitating the connection with the processor LSI is connected to the input terminal of the memory LSI to be stacked thereby increasing the degree of freedom in selecting memories.

    摘要翻译： 随着处理器LSI和存储器之间的转移逐年增加，需要增加通信量并降低通信所需的功率。 由于这是条件，因此考虑了堆叠LSI从而减少通信距离的方法。 然而，本发明人已经发现，对于处理器LSI和存储器LSI的简单堆叠，需要堆叠处理中的成本的降低和要堆叠的存储器LSI的选择的自由度的增加。 一种外部通信LSI，包括用于以高于1GHz的高速率与堆叠的LSI的外部进行通信的电路; 包括通用CPU等的处理器LSI; 并且依次堆叠包括DRAM等的存储器LSI，并且这些LSI通过硅通孔彼此连接，以使得能够以最短路径进行高速和高容量的通信。 此外，用于促进与处理器LSI的连接的插入器连接到要堆叠的存储器LSI的输入端，从而增加选择存储器的自由度。

    Semiconductor apparatus
    26.
    发明授权
    Semiconductor apparatus 有权
    半导体装置

    公开(公告)号：US08184463B2

    公开(公告)日：2012-05-22

    申请号：US12636758

    申请日：2009-12-13

    申请人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

    发明人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

    IPC分类号： G11C5/06 ,  G11C7/00 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

    摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

    摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。

    Semiconductor device and semiconductor integrated circuit
    27.
    发明授权
    Semiconductor device and semiconductor integrated circuit 有权
    半导体器件和半导体集成电路

    公开(公告)号：US08054871B2

    公开(公告)日：2011-11-08

    申请号：US12370338

    申请日：2009-02-12

    申请人： Makoto Saen ,  Kenichi Osada ,  Shigenobu Komatsu ,  Itaru Nonomura ,  Yasuhisa Shimazaki

    发明人： Makoto Saen ,  Kenichi Osada ,  Shigenobu Komatsu ,  Itaru Nonomura ,  Yasuhisa Shimazaki

    IPC分类号： H04L5/16 ,  H04B1/38

    CPC分类号： H01L25/0657 ,  H01L24/16 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

    摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.

    摘要翻译： 一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。 每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。 用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。

    Semiconductor device for synchronous communication between stacked LSI
    28.
    发明授权
    Semiconductor device for synchronous communication between stacked LSI 有权
    用于堆叠LSI之间的同步通信的半导体器件

    公开(公告)号：US07994822B2

    公开(公告)日：2011-08-09

    申请号：US12690659

    申请日：2010-01-20

    申请人： Kazuo Otsuga ,  Kenichi Osada ,  Makoto Saen

    发明人： Kazuo Otsuga ,  Kenichi Osada ,  Makoto Saen

    IPC分类号： H03K19/00

    CPC分类号： H03L7/0812 ,  G06F1/12 ,  H01L25/18 ,  H01L2224/48137 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H03K5/15033 ,  H03L7/07

    摘要： The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.

    摘要翻译： 通过在堆叠的计算LSI之间同步通信和计算，可以提高整个系统的性能。 堆叠的外部通信LSI和计算LSI中的每一个具有将晶体振荡器时钟信号相乘的PLL，分配时钟信号的时钟脉冲发生器和触发器电路。 计算LSI具有由时钟相位比较器，延迟控制器和延迟链组成的DLL电路。 为了同步外部通信LSI和计算LSI的通信和计算，同步参考时钟信号从外部通信LSI经由通孔发送到计算LSI。 计算LSI的内部时钟信号与来自外部通信LSI的同步基准时钟信号通过DLL电路同步。

    Semiconductor integrated circuit and semiconductor device with the same
    30.
    发明授权
    Semiconductor integrated circuit and semiconductor device with the same 有权
    半导体集成电路和半导体器件相同

    公开(公告)号：US07849237B2

    公开(公告)日：2010-12-07

    申请号：US12172512

    申请日：2008-07-14

    申请人： Itaru Nonomura ,  Makoto Saen ,  Kenichi Osada

    发明人： Itaru Nonomura ,  Makoto Saen ,  Kenichi Osada

    IPC分类号： G06F13/12

    CPC分类号： G06F13/4045 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router.

    摘要翻译： 一种互连配置技术，其通过使用3D耦合技术发送和接收通过内置在半导体芯片中的互连的芯片传输的分组，从安装在半导体芯片上的IP到安装在另一半导体芯片上的IP进行访问。 根据该技术的设备具有用于发送接入请求的发起者，用于接收接入请求并发送接入响应的目标，用于中继接入请求和接入响应的路由器，以及3D耦合电路（三维收发机 ），用于与外部进行通信，其中所述3D耦合电路邻近所述路由器设置。