公开(公告)号：US20070090416A1

公开(公告)日：2007-04-26

申请号：US11238447

申请日：2005-09-28

申请人： Brian Doyle ,  Been-Yih Jin ,  Jack Kavalieros ,  Suman Datta ,  Justin Brask ,  Robert Chau

发明人： Brian Doyle ,  Been-Yih Jin ,  Jack Kavalieros ,  Suman Datta ,  Justin Brask ,  Robert Chau

IPC分类号： H01L29/76

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

公开(公告)号：US20070063306A1

公开(公告)日：2007-03-22

申请号：US11234014

申请日：2005-09-22

申请人： Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Suman Datta ,  Robert Chau

发明人： Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Suman Datta ,  Robert Chau

IPC分类号： H01L27/095

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/2022 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/785

摘要： Embodiments of the invention provide a substrate with a surface having different crystal orientations in different areas. Embodiments of the invention provide a substrate with a portion having a crystal orientation and another portion having a crystal orientation. N— and P-type devices may both be formed on the substrate, with each type of device having the proper crystal orientation for optimum performance.

摘要翻译： 本发明的实施例提供一种具有在不同区域中具有不同晶体取向的表面的基底。 本发明的实施方案提供了具有<100>晶体取向的部分和具有<110>晶体取向的另一部分的基底。 可以在衬底上形成N型和P型器件，每种类型的器件具有适当的晶体取向以实现最佳性能。

公开(公告)号：US20070001173A1

公开(公告)日：2007-01-04

申请号：US11158661

申请日：2005-06-21

申请人： Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert Chau ,  Brian Doyle

发明人： Justin Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert Chau ,  Brian Doyle

IPC分类号： H01L29/10

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

摘要翻译： 对半导体膜的图案化方法进行说明。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US20070145487A1

公开(公告)日：2007-06-28

申请号：US11320309

申请日：2005-12-27

申请人： Jack Kavalieros ,  Justin Brask ,  Suman Datta ,  Brian Doyle ,  Robert Chau

发明人： Jack Kavalieros ,  Justin Brask ,  Suman Datta ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

摘要： Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.

摘要翻译： 本发明的实施例提供具有多个门的装置。 器件金属门的凹槽内的应力材料可能在器件的沟道区域中引起应力，从而提高器件的性能。

公开(公告)号：US20070141790A1

公开(公告)日：2007-06-21

申请号：US11638333

申请日：2006-12-12

申请人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert Chau

发明人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert Chau

IPC分类号： H01L21/336

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/762

摘要： A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

摘要翻译： 描述了在碳纳米管内形成能量阱的结构。 该结构包括掺杂半导体区域和未掺杂的半导体区域。 碳纳米管位于掺杂半导体区域和未掺杂的半导体区域之间。 该结构还包括δ掺杂半导体区域。 未掺杂的半导体区域在碳纳米管和δ掺杂区之间。 该掺杂掺杂的δ掺杂半导体区域与掺杂半导体区域的掺杂相反。

公开(公告)号：US20070111419A1

公开(公告)日：2007-05-17

申请号：US11649545

申请日：2007-01-03

申请人： Brian Doyle ,  Been-Yin Jin ,  Jack Kavalieros ,  Suman Datta ,  Justin Brask ,  Robert Chau

发明人： Brian Doyle ,  Been-Yin Jin ,  Jack Kavalieros ,  Suman Datta ,  Justin Brask ,  Robert Chau

IPC分类号： H01L21/8234 ,  H01L29/74

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

公开(公告)号：US20060220074A1

公开(公告)日：2006-10-05

申请号：US11096984

申请日：2005-03-31

申请人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert Chau

发明人： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert Chau

IPC分类号： H01L29/94

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/762

摘要： A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

摘要翻译： 描述了在碳纳米管内形成能量阱的结构。 该结构包括掺杂半导体区域和未掺杂的半导体区域。 碳纳米管位于掺杂半导体区域和未掺杂的半导体区域之间。 该结构还包括δ掺杂半导体区域。 未掺杂的半导体区域在碳纳米管和δ掺杂区之间。 该掺杂掺杂的δ掺杂半导体区域与掺杂半导体区域的掺杂相反。

公开(公告)号：US20060068591A1

公开(公告)日：2006-03-30

申请号：US11240440

申请日：2005-09-29

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian Doyle ,  Justin Brask ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian Doyle ,  Justin Brask ,  Robert Chau

IPC分类号： H01L21/302

CPC分类号： H01L29/42392 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S438/926 ,  Y10S438/957

摘要： A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

摘要翻译： 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许在沟道区下方除去氧化物。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。

公开(公告)号：US20060180859A1

公开(公告)日：2006-08-17

申请号：US11059184

申请日：2005-02-16

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian Doyle ,  Justin Brask ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian Doyle ,  Justin Brask ,  Robert Chau

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L51/0541 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0525

摘要： A top metal gate carbon nanotube transistor may be provided which has acceptable electrical characteristics. The transistor may be formed over a structure including a semiconductor substrate made of an epitaxial layer and covered with an insulating layer. The carbon nanotubes may be deposited thereover, source and drains defined, and a metal gate electrode applied over a high dielectric constant gate dielectric. The processing may be such that the carbon nanotubes are protected from high temperature processing and excessively oxidizing atmospheres.

摘要翻译： 可以提供具有可接受的电特性的顶部金属栅极碳纳米管晶体管。 晶体管可以形成在包括由外延层制成并被绝缘层覆盖的半导体衬底的结构上。 可以在其上沉积碳纳米管，限定源极和漏极，以及施加在高介电常数栅极电介质上的金属栅电极。 处理可以使得碳纳米管被保护免受高温处理和过度氧化的气氛。

公开(公告)号：US20060071275A1

公开(公告)日：2006-04-06

申请号：US10956279

申请日：2004-09-30

申请人： Justin Brask ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

发明人： Justin Brask ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.