公开(公告)号：US20090224309A1

公开(公告)日：2009-09-10

申请号：US12389977

申请日：2009-02-20

申请人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L21/8221 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so that the semiconductor layer infills the first hole and the second hole after the removal of the sacrificing layer

摘要翻译： 一种制造非易失性半导体存储装置的方法，包括：形成第一导电层，使其通过第一绝缘层沿上下方向夹持; 形成第一孔，使其穿透第一绝缘层和第一导电层; 在面向所述第一孔的侧壁上形成第一侧壁绝缘层; 形成牺牲层，使牺牲层填充第一孔; 在牺牲层的上层上形成第二导电层，使得第二导电层在上下方向上被第二绝缘层夹持; 在与所述第一孔匹配的位置上形成第二孔，使得所述第二孔穿过所述第二绝缘层和所述第二导电层; 在面向所述第二孔的侧壁上形成第二侧壁绝缘层; 在形成第二侧壁绝缘层之后去除牺牲层; 以及形成半导体层，使得半导体层在去除牺牲层之后填充第一孔和第二孔

公开(公告)号：US07539056B2

公开(公告)日：2009-05-26

申请号：US11896261

申请日：2007-08-30

申请人： Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Mitsuru Sato

发明人： Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Mitsuru Sato

IPC分类号： G11C16/04

CPC分类号： G11C16/24 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： In a NAND type flash memory, control electrodes of first select transistors in a plurality memory cell units extending along a data line is integrated to constitute a first select signal line while control electrodes of second select transistor are integrated to constitute a second select signal line. The second select signal line is displaced from the first select signal line by a half pitch.

摘要翻译： 在NAND型闪速存储器中，集成了沿着数据线延伸的多个存储单元单元中的第一选择晶体管的控制电极，以构成第一选择信号线，同时第二选择晶体管的控制电极被积分以构成第二选择信号线 。 第二选择信号线从第一选择信号线移位半个间距。

公开(公告)号：US20090101969A1

公开(公告)日：2009-04-23

申请号：US12248577

申请日：2008-10-09

申请人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second insulating film, the gate electrode film and the first insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulator provided on the side surface of the gate opening and having a projecting shape at a portion between the first insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulator, and serving as the one of the source and the drain while being in contact with the first conductive layer; a channel which is buried in the gate opening above the second conductive layer so as to face the gate electrode film with the gate insulator therebetween, and which has a channel layer generated therein, the channel layer allowing majority carriers to flow between the source and the drain in response to a voltage applied to the gate; and a third conductive layer buried in the gate opening above the channel so as to be in contact with the gate insulator to serve as the other one of the source and the drain.

摘要翻译： 一种半导体器件，包括：半导体衬底; 设置在所述基板的表面上并用作源极和漏极之一的第一导电层; 设置在所述第一导电层上的第一绝缘膜; 设置在所述第一绝缘膜上的栅电极膜; 设置在栅电极膜上的第二绝缘膜; 设置为穿透第二绝缘膜的栅极开口，栅极电极膜和第一绝缘膜，以暴露第一导电层的一部分; 设置在所述第一导电层的位于所述栅极开口正下方的表面中的凹部; 栅极绝缘体，其设置在所述栅极开口的侧表面上，并且在所述第一绝缘膜和所述凹部之间的部分处具有突出形状; 第二导电层，其被埋置在所述凹部中并且位于所述栅极开口的底部以与所述栅极绝缘体接触，并且在与所述第一导电层接触的同时用作所述源极和漏极中的一个; 埋入在第二导电层上方的栅极开口中以与门极绝缘体相对的栅极电极膜并且其中产生沟道层的沟道，该沟道层允许多数载流子在源极和源极之间流动 响应于施加到门的电压而漏极; 以及掩埋在沟道上方的栅极开口中的第三导电层，以便与栅极绝缘体接触以用作源极和漏极中的另一个。

公开(公告)号：US20080315291A1

公开(公告)日：2008-12-25

申请号：US12140734

申请日：2008-06-17

申请人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

发明人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/00 ,  H01L21/31

CPC分类号： H01L27/105 ,  H01L21/02161 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31645 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.

摘要翻译： 非易失性半导体存储器件具有多个存储串，每个存储串包括串联连接的多个电可重写存储器单元。 存储器串包括从基板沿垂直方向延伸的柱状半导体部分，与柱状半导体部分相邻形成并构成为积蓄电荷的第一电荷存储层，与第一电荷存储层相邻形成的第一块绝缘体， 第一导体与第一块绝缘体相邻形成。

公开(公告)号：US20080180994A1

公开(公告)日：2008-07-31

申请号：US11955900

申请日：2007-12-13

申请人： Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Masaru Kito ,  Hideaki Aochi ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

发明人： Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Masaru Kito ,  Hideaki Aochi ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

IPC分类号： G11C11/34 ,  H01L29/76 ,  G11C8/00

CPC分类号： H01L27/115 ,  G11C7/18 ,  G11C8/08 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.

摘要翻译： 半导体存储器件具有半导体衬底，形成在所述半导体衬底的表面上的第一选择晶体管，形成在所述第一选择晶体管上方的第一虚拟晶体管，形成在所述第一虚拟晶体管上方的多个存储单元晶体管， 垂直于所述半导体衬底的表面，每个所述存储单元晶体管包括具有电荷累积功能的绝缘层，形成在所述存储单元晶体管上方的第二虚拟晶体管以及形成在所述第二虚设晶体管上方的第二选择晶体管; 其中第一电位被提供给所述第一选择晶体管的栅电极和所述第一虚拟晶体管的栅电极，并且第二电位被提供给所述第二选择晶体管的栅极和所述第二虚设晶体管的栅电极 写入操作的时间将数据写入到所述存储单元晶体管。

公开(公告)号：US20070290253A1

公开(公告)日：2007-12-20

申请号：US11765881

申请日：2007-06-20

申请人： Masaru KITO ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

发明人： Masaru KITO ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42336

摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

摘要翻译： 非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

公开(公告)号：US20070252201A1

公开(公告)日：2007-11-01

申请号：US11654551

申请日：2007-01-18

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L29/76

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US08653577B2

公开(公告)日：2014-02-18

申请号：US13003644

申请日：2009-07-01

申请人： Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh

发明人： Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7926 ,  G11C16/0466 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a stacked body in which insulating films and electrode films are alternately stacked; selection gate electrodes provided on the stacked body; bit lines provided on the selection gate electrodes; semiconductor pillars; connective members separated from one another; and a charge storage layer provided between the electrode film and the semiconductor pillar. One of the connective members is connected between a lower part of one of the semiconductor pillars and a lower part of another of the semiconductor pillars. The one of the semiconductor pillars passes through one of the selection gate electrodes and is connected to one of the bit lines, and the another of the semiconductor pillars passes through another of the selection gate electrodes and is connected to another of the bit lines.

摘要翻译： 非易失性半导体存储器件包括：绝缘膜和电极膜交替层叠的层叠体; 设置在层叠体上的选择栅电极; 设置在选择栅电极上的位线; 半导体柱 连接成员彼此分离; 以及设置在电极膜和半导体柱之间的电荷存储层。 一个连接构件连接在一个半导体柱的下部和另一个半导体柱的下部之间。 半导体柱中的一个穿过选择栅极之一并连接到一个位线，并且另一个半导体柱通过另一个选择栅电极并连接到另一个位线。

公开(公告)号：US08350326B2

公开(公告)日：2013-01-08

申请号：US12839895

申请日：2010-07-20

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/66833

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars. The fifth interconnection is connected to the third interconnection on a side opposite to the selection unit stacked structural body.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构体，第一和第二半导体柱，存储单元连接部分，选择单元堆叠结构体，第一和第二选择单元半导体柱，选择单元连接部分 ，以及第一至第五互连。 半导体支柱刺穿堆叠的结构体。 第一和第二互连分别连接到第一和第二半导体柱。 存储单元连接部连接第一和第二半导体柱。 选择单元半导体柱刺穿选择单元堆叠结构体。 第三和第四互连分别连接到第一和第二选择单元半导体柱。 选择单元连接部分连接第一和第二选择单元半导体柱。 第五互连在与选择单元堆叠结构体相反的一侧连接到第三互连。

公开(公告)号：US08294191B2

公开(公告)日：2012-10-23

申请号：US12943349

申请日：2010-11-10

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构，第一和第二半导体柱，半导体连接部分，第一和第二连接部分导电层，第一和第二柱部存储器 层，第一和第二连接部分存储层。 第一和第二堆叠结构包括在第一方向上交替堆叠的电极膜和电极间绝缘膜。 第二堆叠结构与第一堆叠结构相邻。 第一和第二半导体柱分别刺穿第一和第二堆叠结构。 半导体连接部分连接第一和第二半导体柱。 第一和第二柱部存储层设置在电极膜和半导体柱之间。 第一和第二连接部分存储层设置在连接部分导电层和半导体连接部分之间。