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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
    21.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100200906A1

    公开(公告)日：2010-08-12

    申请号：US12696544

    申请日：2010-01-29

    申请人： Masaru KIDOH ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

    发明人： Masaru KIDOH ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

    IPC分类号： H01L27/112 ,  H01L21/8246

    CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556

    摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer structure; a semiconductor pillar; a third insulating film; and a fourth insulating film layer. The a multilayer structure is provided on the semiconductor substrate and including a plurality of constituent multilayer bodies stacked in a first direction perpendicular to a major surface of the semiconductor substrate. Each of the plurality of constituent multilayer bodies includes an electrode film provided parallel to the major surface, a first insulating film, a charge storage layer provided between the electrode film and the first insulating film, and a second insulating film provided between the charge storage layer and the electrode film. The semiconductor pillar penetrates through the multilayer structure in the first direction. The third insulating film is provided between the semiconductor pillar and the electrode film. The fourth insulating film is provided between the semiconductor pillar and the charge storage layer.

    摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 多层结构; 半导体柱; 第三绝缘膜; 和第四绝缘膜层。 多层结构设置在半导体衬底上，并且包括沿垂直于半导体衬底的主表面的第一方向堆叠的多个构成层叠体。 多个构成多层体中的每一个包括平行于主表面设置的电极膜，第一绝缘膜，设置在电极膜和第一绝缘膜之间的电荷存储层，以及设置在电荷存储层 电极膜。 半导体柱沿第一方向穿透多层结构。 第三绝缘膜设置在半导体柱和电极膜之间。 第四绝缘膜设置在半导体柱和电荷存储层之间。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    26.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20080149913A1

    公开(公告)日：2008-06-26

    申请号：US11962862

    申请日：2007-12-21

    申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Mitsuru Sato

    发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Mitsuru Sato

    IPC分类号： H01L27/105 ,  H01L21/8239 ,  H01L45/00

    CPC分类号： H01L27/2454 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146

    摘要： A semiconductor memory device is disclosed, which includes a first memory cell array formed on a semiconductor substrate and composed of a plurality of memory cells stacked in layers each having a characteristic change element and a vertical type memory cell transistor connected in parallel to each other, a plurality of second memory cell arrays formed on the semiconductor substrate and having the same structure as the first memory cell array, and arranged in an X direction with respect to the first memory cell array, and a plurality of third memory cell arrays formed on the semiconductor substrate and having the same structure as the first memory cell array, and arranged in a Y direction with respect to the first memory cell array, wherein a gate voltage is applied to gates of the vertical type memory cell transistors of the first to third memory cell arrays in a same layer.

    摘要翻译： 公开了一种半导体存储器件，其包括形成在半导体衬底上的第一存储器单元阵列，并且由堆叠成各自具有彼此并联连接的特征变化元件和垂直型存储单元晶体管的多个存储单元组成， 多个第二存储单元阵列，形成在所述半导体衬底上并具有与所述第一存储单元阵列相同的结构，并且相对于所述第一存储单元阵列沿X方向布置;以及多个第三存储单元阵列， 半导体衬底并且具有与第一存储单元阵列相同的结构，并且相对于第一存储单元阵列在Y方向上布置，其中栅极电压被施加到第一至第三存储器的垂直型存储单元晶体管的栅极 单元阵列在同一层。

    Nonvolatile semiconductor memory device and manufacturing method thereof
    27.
    发明申请
    Nonvolatile semiconductor memory device and manufacturing method thereof 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20080067583A1

    公开(公告)日：2008-03-20

    申请号：US11898746

    申请日：2007-09-14

    申请人： Masaru Kidoh ,  Ryota Katsumata ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Masaru Kito

    发明人： Masaru Kidoh ,  Ryota Katsumata ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Masaru Kito

    IPC分类号： H01L29/792 ,  H01L21/4763

    CPC分类号： H01L27/105 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881

    摘要： A nonvolatile semiconductor memory device includes a substrate, and a plurality of memory strings, the memory string including a first selection transistor including a first pillar shaped semiconductor formed perpendicular to the substrate, a first gate insulating film formed around the first pillar shaped semiconductor, and a first gate electrode formed around the first gate insulating film, and a plurality of memory cells including a second pillar shaped semiconductor formed on the first pillar shaped semiconductor, the diameter of the first pillar shaped semiconductor being larger than the diameter of the second pillar shaped semiconductor at the part where the second pillar shaped semiconductor is connected to the first pillar shaped semiconductor, a first insulating film formed around the second pillar shaped semiconductor, a charge storage layer formed around the first insulating film, a second insulating film formed around the charge storage layer, and first to nth electrodes formed around the second insulating film (n is a natural number not less than 2), the first to nth electrodes being plate shaped, the first to nth electrodes being first to nth conductor layers spread in two dimensions, and a second selection transistor including a third pillar shaped semiconductor formed on the second pillar shaped semiconductor, a second gate insulating film formed around the third pillar shaped semiconductor and a second gate electrode formed around the second gate insulating film.

    摘要翻译： 非易失性半导体存储器件包括衬底和多个存储器串，所述存储器串包括第一选择晶体管，所述第一选择晶体管包括垂直于所述衬底形成的第一柱状半导体，围绕所述第一柱状半导体形成的第一栅极绝缘膜，以及 形成在第一栅极绝缘膜周围的第一栅电极和形成在第一柱状半导体上的包括第二柱状半导体的多个存储单元，第一柱状半导体的直径大于第二柱状半导体的直径 在第二柱状半导体与第一柱状半导体连接的部分处的半导体，形成在第二柱状半导体周围的第一绝缘膜，形成在第一绝缘膜周围的电荷存储层，形成在电荷周围的第二绝缘膜 存储层和第一至第n电极fo 围绕第二绝缘膜（n是不小于2的自然数），第一至第n电极是板状的，第一至第n电极是第一至第n导体层在二维上扩展，第二选择晶体管包括 形成在第二柱状半导体上的第三柱状半导体，围绕第三柱状半导体形成的第二栅极绝缘膜和形成在第二栅极绝缘膜周围的第二栅电极。

    Semiconductor device and method of manufacturing the same
    28.
    发明申请
    Semiconductor device and method of manufacturing the same 失效

    公开(公告)号：US20060189070A1

    公开(公告)日：2006-08-24

    申请号：US11117337

    申请日：2005-04-29

    申请人： Masaru Kidoh ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Hitomi Yasutake

    发明人： Masaru Kidoh ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Hitomi Yasutake

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10841 ,  H01L27/10867 ,  H01L27/10882

    摘要： A semiconductor device includes a semiconductor substrate, a trench formed in the semiconductor substrate, an island-like element region formed in the semiconductor substrate, having an upper surface, first to third side surfaces, an upper portion, a middle portion and a lower portion, a gate insulating film formed on the first to third side surfaces in the upper portion of the element region, a gate electrode having first and second bottom surfaces, a first diffusion layer formed along the upper surface of the element region, a second diffusion layer formed along the first side surface in the middle portion of the element region, a channel region having first to third regions formed along the first to third side surfaces in the upper portion of the element region, a capacitor formed in the trench, and a bit line electrically connected to the first diffusion layer.

    Semiconductor device
    29.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20060145228A1

    公开(公告)日：2006-07-06

    申请号：US11311268

    申请日：2005-12-20

    申请人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Nobutoshi Aoki ,  Masaki Kondo ,  Sanae Ito

    发明人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Nobutoshi Aoki ,  Masaki Kondo ,  Sanae Ito

    IPC分类号： H01L29/94

    CPC分类号： H01L29/66651 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/1037 ,  H01L29/945

    摘要： A semiconductor memory device comprising a semiconductor substrate, element isolating regions formed on the semiconductor substrate, an element forming region provided between the element isolating regions on the semiconductor substrate, the element forming region having a protruding portion, a transistor having a channel formed in the protruding portion of the element forming region, and a capacitor formed in or on the semiconductor substrate to be connected to the transistor, wherein the protruding portion in the element forming region includes first and second inclined and opposed planes arranged along a channel width direction of the transistor, and an upper plane provided between the first and second inclined planes.

    摘要翻译： 一种半导体存储器件，包括半导体衬底，形成在半导体衬底上的元件隔离区域，设置在半导体衬底上的元件隔离区域之间的元件形成区域，具有突出部分的元件形成区域， 所述元件形成区域的突出部分和形成在所述半导体衬底中或与所述晶体管连接的电容器，其中所述元件形成区域中的所述突出部分包括沿着所述晶体管的沟道宽度方向布置的第一和第二倾斜和相对的平面 晶体管，以及设置在第一和第二倾斜平面之间的上平面。

    Non-volatile semiconductor storage device and method of manufacturing the same
    30.
    发明授权
    Non-volatile semiconductor storage device and method of manufacturing the same 有权
    非易失性半导体存储装置及其制造方法

    公开(公告)号：US08728919B2

    公开(公告)日：2014-05-20

    申请号：US13723601

    申请日：2012-12-21

    申请人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

    发明人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

    IPC分类号： H01L21/20

    CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

    摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

    摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。