公开(公告)号：US09076820B2

公开(公告)日：2015-07-07

申请号：US13600373

申请日：2012-08-31

申请人： Soichiro Kitazaki ,  Masaru Kidoh ,  Mitsuru Sato ,  Ryota Katsumata ,  Tadashi Iguchi

发明人： Soichiro Kitazaki ,  Masaru Kidoh ,  Mitsuru Sato ,  Ryota Katsumata ,  Tadashi Iguchi

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7827

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of insulating isolation sections provided so as to extend in a first direction, isolate the stacked body in a second direction, and have a projection projecting from the stacked body. Each insulating isolation section has a side wall including recessed sections and projected sections repeated along the first direction. The method includes forming a sidewall film on a side wall of the projection of the insulating isolation section, and forming a plurality of first holes surrounded by the sidewall film and isolated by the sidewall film in the first direction, between the plurality of insulating isolation sections. The method includes forming a second hole in the stacked body provided under the first hole by etching with the insulating isolation section and the sidewall film used as a mask.

摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括形成多个绝缘隔离部分，其被设置为沿第一方向延伸，使堆叠体沿第二方向隔离，并具有从堆叠体突出的突出部。 每个绝缘隔离部分具有侧壁，该侧壁包括沿着第一方向重复的凹陷部分和突出部分。 该方法包括在绝缘隔离部分的突起的侧壁上形成侧壁膜，并且在多个绝缘隔离部分之间形成由侧壁膜围绕并由第一方向隔离的多个第一孔 。 该方法包括通过用绝缘隔离部分和用作掩模的侧壁膜进行蚀刻，在设置在第一孔下方的层叠体中形成第二孔。

公开(公告)号：US08659070B2

公开(公告)日：2014-02-25

申请号：US12561451

申请日：2009-09-17

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kido ,  Masaru Kito ,  Mitsuru Sato

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kido ,  Masaru Kito ,  Mitsuru Sato

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7881 ,  H01L29/7926

摘要： The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.

摘要翻译： 本发明的半导体存储器件包括具有串联连接的多个电可再编程存储器单元的多个存储器串，具有列形半导体的存储器串，形成在柱状半导体周围的第一绝缘膜，电荷累积层 形成在第一绝缘膜周围，形成在电荷累积膜周围的第二绝缘膜和围绕第二绝缘膜形成的多个电极，经由多个选择晶体管连接到存储器串的一端的位线，以及导电 分别在存储器串的多个电极和不同的存储器串的多个电极中分别共享，其中导电层的每个端部在平行于位线的方向上形成为台阶形状 。

公开(公告)号：US08253187B2

公开(公告)日：2012-08-28

申请号：US12142289

申请日：2008-06-19

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

IPC分类号： H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11556

摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

公开(公告)号：US20080315296A1

公开(公告)日：2008-12-25

申请号：US12142289

申请日：2008-06-19

申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11556

摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

公开(公告)号：US20080219054A1

公开(公告)日：2008-09-11

申请号：US12039461

申请日：2008-02-28

申请人： Fumitaka ARAI ,  Masaru Kito ,  Mitsuru Sato

发明人： Fumitaka ARAI ,  Masaru Kito ,  Mitsuru Sato

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion which is provided between one-side terminal end portions of two active areas neighboring in a second direction that crosses the first direction, and a second extension portion which is provided between other-side terminal end portions of the two active areas neighboring in the second direction, the first and second extension portions connecting the two active areas in a loop configuration.

摘要翻译： 半导体存储器件包括多个有源区，每个有源区各自沿第一方向延伸，并且包括存储单元串，该存储单元串包括选择晶体管和存储单元，其电流通路串联连接，第一延伸部分设置在一侧 在与第一方向相反的第二方向上相邻的两个有效区域的末端部分和设置在与第二方向相邻的两个有效区域的另一侧终端部分之间的第二延伸部分，第一和第二延伸部分 以循环配置连接两个活动区域。

公开(公告)号：US07091546B2

公开(公告)日：2006-08-15

申请号：US11038173

申请日：2005-01-21

申请人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

发明人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

IPC分类号： H01L29/772

CPC分类号： H01L27/10867

摘要： A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor formed so as to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底中的沟槽电容器，形成为沟槽电容器的单元晶体管，并且具有形成在半导体衬底上的栅极电极和形成在半导体衬底的表面中的源极/漏极区域 形成在半导体衬底中以便电连接在沟槽电容器和源极/漏极区之间的杂质扩散区域和形成在杂质扩散区域和沟槽电容器之间的Ge包含区域。

公开(公告)号：US20080017992A1

公开(公告)日：2008-01-24

申请号：US11826224

申请日：2007-07-13

申请人： Masaru Kito ,  Mitsuru Sato ,  Yuzo Nagata ,  Koji Hashimoto

发明人： Masaru Kito ,  Mitsuru Sato ,  Yuzo Nagata ,  Koji Hashimoto

IPC分类号： H01L21/311 ,  H01L23/48

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L27/105 ,  H01L27/1052

摘要： A first hard mask is formed on a polysilicon film or a target member to be etched, on which a second hard mask composed of amorphous silicon is formed. Ions of boron or the like are implanted into a desired portion of the second hard mask, and then the first hard mask is etched with a mask of the second hard mask. Only the portion not ion-implanted of the second hard mask is etched off by wet etching. A sidewall film is formed on sidewalls of the first hard mask, and then the first hard mask having an upper portion exposed, not covered with the second hard mask is selectively etched off.

摘要翻译： 第一硬掩模形成在多晶硅膜或要蚀刻的靶构件上，在其上形成由非晶硅构成的第二硬掩模。 将硼等的离子注入到第二硬掩模的期望部分中，然后用第二硬掩模的掩模蚀刻第一硬掩模。 通过湿式蚀刻仅蚀刻第二硬掩模未离子注入的部分。 在第一硬掩模的侧壁上形成侧壁膜，然后选择性地蚀刻除去未被第二硬掩模覆盖的具有暴露的上部的第一硬掩模。

公开(公告)号：US07813203B2

公开(公告)日：2010-10-12

申请号：US12039461

申请日：2008-02-28

申请人： Fumitaka Arai ,  Masaru Kito ,  Mitsuru Sato

发明人： Fumitaka Arai ,  Masaru Kito ,  Mitsuru Sato

IPC分类号： G11C7/02

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion which is provided between one-side terminal end portions of two active areas neighboring in a second direction that crosses the first direction, and a second extension portion which is provided between other-side terminal end portions of the two active areas neighboring in the second direction, the first and second extension portions connecting the two active areas in a loop configuration.

摘要翻译： 半导体存储器件包括多个有源区，每个有源区各自沿第一方向延伸，并且包括存储单元串，该存储单元串包括选择晶体管和存储单元，其电流通路串联连接，第一延伸部分设置在一侧 在与第一方向相反的第二方向上相邻的两个有效区域的末端部分和设置在与第二方向相邻的两个有效区域的另一侧终端部分之间的第二延伸部分，第一和第二延伸部分 以循环配置连接两个活动区域。

公开(公告)号：US20050184323A1

公开(公告)日：2005-08-25

申请号：US11038173

申请日：2005-01-21

申请人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

发明人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/10

CPC分类号： H01L27/10867

摘要： A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor adjacently formed to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底中的沟槽电容器，与沟槽电容器相邻形成并具有形成在半导体衬底上的栅极电极和形成在半导体衬底的表面中的源极/漏极区域的单元晶体管， 形成在半导体衬底中以便电连接在沟槽电容器和源极/漏极区域之间的杂质扩散区域和形成在杂质扩散区域和沟槽电容器之间的Ge包含区域。

公开(公告)号：US07838996B2

公开(公告)日：2010-11-23

申请号：US11826709

申请日：2007-07-18

申请人： Mitsuru Sato ,  Masaru Kito ,  Yuzo Nagata

发明人： Mitsuru Sato ,  Masaru Kito ,  Yuzo Nagata

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76838 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/0203 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a wiring layer. The wiring layer is provided by forming a sidewall film having a closed-loop along a sidewall of a hard mask, etching off the hard mask to leave the sidewall film, and then etching a target material to be etched with a mask of the sidewall film. The wiring layer includes a folded wiring section formed along an end of the hard mask, and a parallel section composed of two parallel wires continued from the folded wiring section. The wiring layer has a closed-loop cut made in a portion except for the folded wiring section and the parallel section. The folded wiring section and the parallel section are used as a contact region for connection to another wire.

摘要翻译： 半导体器件包括布线层。 布线层通过沿着硬掩模的侧壁形成具有闭环的侧壁膜，蚀刻出硬掩模以离开侧壁膜，然后用侧壁膜的掩模蚀刻待蚀刻的目标材料来提供 。 布线层包括沿着硬掩模的端部形成的折叠布线部分和由折叠的布线部分连续的两条平行的线构成的平行部分。 布线层具有除了折叠布线部分和平行部分之外的部分中的闭环切割。 折叠的布线部分和平行部分用作用于连接到另一导线的接触区域。