公开(公告)号：US06552790B1

公开(公告)日：2003-04-22

申请号：US09788905

申请日：2001-02-20

申请人： Michael K. Templeton ,  Bharath Rangarajan

发明人： Michael K. Templeton ,  Bharath Rangarajan

IPC分类号： G01B1100

CPC分类号： G03F7/70633 ,  G03F9/7003 ,  G03F9/7076 ,  G03F9/7084

摘要： The present invention relates to wafer alignment. A reticle is employed which includes, a design, and a first and second set of scribe marks. The first and second sets of scribe marks have an associated symmetry relative to the reticle design. The design and scribe marks are printed at selected field locations on a surface layer of the wafer. The first and second sets of scribe marks as printed at adjacent fields on the surface layer of wafer form a composite set of scribe marks. The symmetric relationship between the first and second sets of scribe marks results in the composite set of scribe marks substantially negating print errors of the marks due to reticle rotation and/or lens magnification with respect to a geometric reference point of the composite set of scribe marks. The employment of the composite set of scribe marks, such as to locate a corresponding virtual alignment mark, substantially facilitates mitigation of overlay error in wafer alignment.

摘要翻译： 本发明涉及晶圆对准。 使用掩模版，其包括设计，以及第一和第二组划线标记。 第一组和第二组划痕具有相对于标线设计的相关对称性。 设计和划痕被印在晶片的表面层上的选定的场地。 在晶片表面层上的相邻场印刷的第一组和第二组刻痕形成一组复合的划线标记。 第一组和第二组划线标记之间的对称关系导致划线标记的复合组合基本上抵消了由于标线转动和/或透镜倍率而导致的标记的印刷误差相对于复合组划线标记的几何参考点 。 使用复合组划线标记，例如定位相应的虚拟对准标记，基本上有助于减轻晶片对准中的重叠误差。

公开(公告)号：US06524944B1

公开(公告)日：2003-02-25

申请号：US09617374

申请日：2000-07-17

申请人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Michael K. Templeton

发明人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Michael K. Templeton

IPC分类号： H01L214763

CPC分类号： H01L21/7682

摘要： One aspect of the present invention relates to a method of forming an advanced low k material between metal lines on a semiconductor substrate, involving the steps of providing the semiconductor substrate having a plurality of metal lines thereon; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; and at least one of heating or etching the semiconductor substrate whereby at least a portion of the spin-on material is removed, thereby forming the advanced low k material comprising at least one air void between the metal lines, the advanced low k material having a dielectric constant of about 2 or less. Another aspect of the present invention relates to a method of forming a semiconductor structure, involving the steps of forming a first plurality of metal lines on the semiconductor structure; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; forming a plurality of openings in the spin-on material exposing a portion of the metal lines and depositing metal to form a plurality of metal vias in the openings; forming a second plurality of metal lines over at least a portion of the metal vias; and at least one of heating or etching the semiconductor structure whereby at least a portion of the spin-on material is removed, thereby forming an advanced low k material comprising at least one air void, the advanced low k material having a dielectric constant of about 2 or less.

摘要翻译： 本发明的一个方面涉及一种在半导体衬底上的金属线之间形成高级低k材料的方法，包括提供其上具有多条金属线的半导体衬底的步骤; 在其上具有多条金属线的半导体衬底上沉积旋涂材料; 以及加热或蚀刻半导体衬底中的至少一个，由此除去旋涂材料的至少一部分，从而形成包括金属线之间的至少一个空气空隙的高级低k材料，先进的低k材料具有 介电常数约为2或更小。 本发明的另一方面涉及一种形成半导体结构的方法，包括在半导体结构上形成第一多个金属线的步骤; 在其上具有多条金属线的半导体衬底上沉积旋涂材料; 在所述旋涂材料中形成暴露金属线的一部分并沉积金属以在所述开口中形成多个金属通孔的多个开口; 在所述金属通孔的至少一部分上形成第二多个金属线; 以及加热或蚀刻半导体结构中的至少一个，由此除去旋涂材料的至少一部分，从而形成包括至少一个空气空隙的先进的低k材料，该介电常数为约 2以下。

公开(公告)号：US06444381B1

公开(公告)日：2002-09-03

申请号：US09729295

申请日：2000-12-04

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan ,  Khoi A. Phan ,  Bryan K. Choo ,  Sanjay K. Yedur

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan ,  Khoi A. Phan ,  Bryan K. Choo ,  Sanjay K. Yedur

IPC分类号： G03F900

CPC分类号： G03F1/74 ,  Y10S430/143

摘要： One aspect of the present invention relates to a method for reducing carbon contamination on a mask involving placing a mask plate having carbon-containing contaminants thereon in a processing chamber; simultaneously contacting the mask plate with oxygen and exposing the mask plate with a flood exposure of electron beams wherein the carbon-containing contaminants are converted to a by-product; and removing the by-product from the processing chamber.

摘要翻译： 本发明的一个方面涉及一种用于减少掩模上的碳污染的方法，其涉及将具有含碳污染物的掩模板放置在处理室中; 同时使掩模板与氧气接触，并将电子束的暴露暴露于掩模板，其中含碳污染物转化为副产物; 并从处理室中除去副产物。

公开(公告)号：US06423650B1

公开(公告)日：2002-07-23

申请号：US09371715

申请日：1999-08-09

申请人： Marina V. Plat ,  Christopher F. Lyons ,  Michael K. Templeton ,  Bhanwar Singh

发明人： Marina V. Plat ,  Christopher F. Lyons ,  Michael K. Templeton ,  Bhanwar Singh

IPC分类号： H01L2131

摘要： In one embodiment, the present invention relates to a method of processing a semiconductor substrate, involving the steps of providing the semiconductor substrate having an upper surface; roughening the upper surface of the semiconductor substrate so that the upper surface of the semiconductor substrate has an Rtm of about 10 Å or more; and depositing an ultra-thin photoresist on the upper surface of the semiconductor substrate, the ultra-thin photoresist having a thickness of about 2,000 Å or less.

公开(公告)号：US06335152B1

公开(公告)日：2002-01-01

申请号：US09564408

申请日：2000-05-01

申请人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

发明人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

IPC分类号： G03F738

CPC分类号： G03F7/38

摘要： In one embodiment, the present invention relates to a method of processing an irradiated photoresist involving the steps of placing a substrate having the irradiated photoresist thereon at a first temperature in a rapid thermal anneal furnace; heating the substrate having the irradiated photoresist thereon to a second temperature within about 0.1 seconds to about 10 seconds; cooling the substrate having the irradiated photoresist thereon to a third temperature in a rapid thermal annealing furnace within about 0.1 seconds to about 10 seconds; and developing the irradiated photoresist, wherein the second temperature is higher than the first temperature and the third temperature. In another embodiment, the present invention relates to a system of processing a photoresist, containing a source of actinic radiation and a mask for selectively irradiating a photoresist; a rapid thermal annealing furnace for rapidly heating and rapidly cooling a selectively irradiated photoresist, wherein the rapid heating and rapid cooling are independently conducted within about 0.1 seconds to about 10 seconds; and a developer for developing a rapid thermal annealing furnace heated and selectively irradiated photoresist into a patterned photoresist.

摘要翻译： 在一个实施方案中，本发明涉及一种处理被照射的光致抗蚀剂的方法，包括以下步骤：在快速热退火炉中将具有照射光致抗蚀剂的基底在第一温度下放置; 将其上具有照射的光致抗蚀剂的基板加热至约0.1秒至约10秒的第二温度; 将快速热退火炉中具有照射光致抗蚀剂的基板冷却至约0.1秒至约10秒的第三温度; 并且显影所述被照射的光致抗蚀剂，其中所述第二温度高于所述第一温度和所述第三温度。 在另一个实施方案中，本发明涉及一种处理含有光化辐射源的光致抗蚀剂的系统和用于选择性地照射光致抗蚀剂的掩模; 快速热退火炉，用于快速加热和快速冷却选择性照射的光致抗蚀剂，其中快速加热和快速冷却在约0.1秒至约10秒内独立进行; 以及用于将快速热退火炉加热并选择性地照射光致抗蚀剂的显影剂加工成图案化的光致抗蚀剂。

公开(公告)号：US06245493B1

公开(公告)日：2001-06-12

申请号：US09205738

申请日：1998-12-04

申请人： Bhanwar Singh ,  Bharath Rangarajan ,  Sanjay K. Yedur ,  Michael K. Templeton ,  Christopher F. Lyons

发明人： Bhanwar Singh ,  Bharath Rangarajan ,  Sanjay K. Yedur ,  Michael K. Templeton ,  Christopher F. Lyons

IPC分类号： G03F700

CPC分类号： H01L21/0276 ,  G03F7/091 ,  G03F7/16 ,  H01L21/3105

摘要： A method for creating a roughened surface on a material exposed to light during a photolithographic process is provided. The roughened surface is created on a surface of the material via a plasma etch process. The roughened surface diffuses light incident to the material such that the diffused light causes insubstantial damage to a photoresist subsequently formed on the material.

摘要翻译： 提供了一种在光刻过程中在暴露于光的材料上产生粗糙表面的方法。 通过等离子体蚀刻工艺在材料的表面上形成粗糙表面。 粗糙表面扩散入射到材料的光，使得漫射的光对随后在材料上形成的光致抗蚀剂造成非实质的损坏。

公开(公告)号：US06238830B1

公开(公告)日：2001-05-29

申请号：US09429994

申请日：1999-10-29

申请人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

发明人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

IPC分类号： G03F900

CPC分类号： G03F7/70875 ,  G01Q30/10 ,  G01Q80/00 ,  H01J2237/31759 ,  Y10S977/855

摘要： A system for monitoring and regulating a photoresist temperature in a maskless lithography pattern transfer process is disclosed. The system includes a photoresist layer overlying a substrate and a material associated with the photoresist layer, wherein the material exhibits a transformation over variations in temperature. The system also includes a detection system for detecting the transformation in the material and a processor operatively coupled to the detection system. The processor receives information associated with the detected transformation and uses the information to control a tool being used for the pattern transfer, thereby reducing variations in temperature in the resist during pattern transfer. In addition, a method of monitoring and regulating a photoresist temperature in a maskless lithography pattern transfer process is disclosed. The method includes associating a material having a characteristic which varies over variations in temperature with a photoresist layer which overlies a substrate and detecting the characteristic during the pattern transfer process. Once detected a temperature of a portion of the photoresist layer is determined using the detected characteristic and an operation of a writing tool which performs the pattern transfer process in response to the photoresist layer temperature is controlled in response thereto.

摘要翻译： 公开了一种用于在无掩模光刻图案转印工艺中监测和调节光刻胶温度的系统。 该系统包括覆盖衬底的光致抗蚀剂层和与光致抗蚀剂层相关联的材料，其中材料表现出与温度变化的转变。 该系统还包括用于检测材料中的变换的检测系统和可操作地耦合到检测系统的处理器。 处理器接收与检测到的变换相关联的信息，并使用该信息来控制用于图案转印的工具，由此减少图案转印期间抗蚀剂的温度变化。 此外，公开了一种在无掩模光刻图案转印工艺中监测和调节光刻胶温度的方法。 该方法包括将具有随温度变化变化的特性的材料与覆盖在衬底上的光致抗蚀剂层相关联，并且在图案转移过程期间检测特性。 一旦检测到，使用检测到的特性确定光刻胶层的一部分的温度，并响应于光致抗蚀剂层温度来控制执行图案转印处理的写入工具的操作。

公开(公告)号：US07943289B2

公开(公告)日：2011-05-17

申请号：US11087011

申请日：2005-03-22

申请人： Bharath Rangarajan ,  Michael K. Templeton ,  Ramkumar Subramanian

发明人： Bharath Rangarajan ,  Michael K. Templeton ,  Ramkumar Subramanian

IPC分类号： G03F7/20

CPC分类号： H01L21/0331 ,  G03F7/40 ,  H01L21/0272 ,  H01L21/0274

摘要： The invention provides systems and processes that form the inverse (photographic negative) of a patterned first coating. The patterned first coating is usually provided by a resist. After the first coating is patterned, a coating of a second material is provided thereover. The uppermost layer of the second coating is removed, where appropriate, to expose the patterned first coating. The patterned first coating is subsequently removed, leaving the second coating material in the form of a pattern that is the inverse pattern of the first coating pattern. The process may be repeated with a third coating material to reproduce the pattern of the first coating in a different material. Prior to applying the second coating, the patterned first coating may be trimmed by etching, thereby reducing the feature size and producing sublithographic features. In addition to providing sublithographic features, the invention gives a simple, efficient, and high fidelity method of obtaining inverse coating patterns.

摘要翻译： 本发明提供了形成图案化的第一涂层的逆（照相负）的系统和工艺。 图案化的第一涂层通常由抗蚀剂提供。 在对第一涂层进行图案化之后，在其上提供第二材料的涂层。 在适当的情况下去除第二涂层的最上层以暴露图案化的第一涂层。 随后去除图案化的第一涂层，留下作为第一涂层图案的相反图案的图案形式的第二涂层材料。 可以用第三涂层材料重复该过程，以以不同的材料再现第一涂层的图案。 在施加第二涂层之前，可以通过蚀刻修整图案化的第一涂层，从而减小特征尺寸并产生亚光刻特征。 除了提供亚光刻特征之外，本发明还提供了一种简单，有效和高保真的获得反涂层图案的方法。

公开(公告)号：US06828162B1

公开(公告)日：2004-12-07

申请号：US09894434

申请日：2001-06-28

申请人： Arvind Halliyal ,  Bhanwar Singh ,  Michael K. Templeton ,  Ramkumar Subramanian

发明人： Arvind Halliyal ,  Bhanwar Singh ,  Michael K. Templeton ,  Ramkumar Subramanian

IPC分类号： H01L2100

CPC分类号： H01L21/67253 ,  G01N21/4738 ,  H01L21/02129 ,  H01L21/31625

摘要： A system for monitoring and controlling a boron phosphorous doped silicon oxide (BPSG) deposition and reflow process is provided. The system includes one or more light sources, each light source directing light to one or more portions of a wafer upon which BPSG is deposited. Light reflected from the BPSG is collected by a measuring system, which processes the collected light. Light passing through the BPSG may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the conformality of the BPSG deposition of the respective portions of the wafer. The measuring system provides BPSG deposition related data to a processor that determines the BPSG deposition of the respective portions of the wafer. The system also includes a plurality of reflow controlling devices, each such device corresponding to a respective portion of the wafer and providing for the heating and/or cooling thereof. The processor selectively controls the reflow controlling devices so as to regulate temperature of the respective portions of the wafer.

摘要翻译： 提供了一种用于监测和控制硼磷掺杂氧化硅（BPSG）沉积和回流工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到沉积BPSG的晶片的一个或多个部分。 从BPSG反射的光被测量系统收集，该系统处理收集的光。 通过BPSG的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的BPSG沉积的一致性。 测量系统将BPSG沉积相关数据提供给确定晶片各部分的BPSG沉积的处理器。 该系统还包括多个回流控制装置，每个这样的装置对应于晶片的相应部分并提供加热和/或冷却。 处理器选择性地控制回流控制装置，以便调节晶片各部分的温度。

公开(公告)号：US06774989B1

公开(公告)日：2004-08-10

申请号：US10050453

申请日：2002-01-16

申请人： Bharath Rangarajan ,  Michael K. Templeton ,  Arvind Halliyal ,  Bhanwar Singh

发明人： Bharath Rangarajan ,  Michael K. Templeton ,  Arvind Halliyal ,  Bhanwar Singh

IPC分类号： G01N2100

CPC分类号： G01N21/956 ,  G01N21/47

摘要： A system for detecting voids in an ILD layer is provided. The system includes one or more light sources, each light source directing light to respective portions of the ILD layer. Light reflected from the respective portions is collected by a measuring system that processes the collected light. The collected light is indicative of the presence of voids in the respective portions of the ILD layer. The measuring system provides ILD layer void related data to a processor that determines whether voids exist in the respective portions of the ILD layer. The processor selectively marks the ILD layer portions to facilitate further processing and/or destruction of the IC with the ILD layer voids.

摘要翻译： 提供一种用于检测ILD层中的空隙的系统。 该系统包括一个或多个光源，每个光源将光引导到ILD层的相应部分。 通过处理收集的光的测量系统收集从各个部分反射的光。 收集的光指示在ILD层的各个部分中存在空隙。 测量系统向处理器提供ILD层空隙相关数据，该处理器确定在ILD层的相应部分中是否存在空隙。 处理器选择性地标记ILD层部分以促进具有ILD层空隙的IC的进一步处理和/或破坏。