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21.发明授权Quantization noise coupling delta sigma ADC with a delay in the main DAC feedback 有权量化噪声耦合ΔΣADC在主DAC反馈中具有延迟公开(公告)号：US09054733B2
公开(公告)日：2015-06-09
申请号：US14301948
申请日：2014-06-11
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix , Fabien Vaucher
IPC: H03M3/00
Abstract: A delta-sigma modulator has a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function, a second summing point adding an output signal from said transfer function to the input signal and subtracting a second feedback signal, a first integrator receiving an output signal from the second summing point, a quantizer receiving an output signal from the integrator and generating an output bitstream, and a digital-to-analog converter receiving the bitstream, wherein the first and second feedback signal are the output signal from said digital-to-analog converter delayed by a one sample delay.
Abstract translation: Δ-Σ调制器具有从输入信号减去第一反馈信号并将结果转发到传递函数的第一求和点，将来自所述传递函数的输出信号加到输入信号的第二求和点，并且减去第二反馈信号 接收来自第二求和点的输出信号的第一积分器，接收来自积分器的输出信号并产生输出比特流的量化器以及接收比特流的数模转换器，其中第一和第二反馈信号是 来自所述数模转换器的输出信号延迟一个采样延迟。
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公开(公告)号：US20140253354A1
公开(公告)日：2014-09-11
申请号：US14197401
申请日：2014-03-05
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
IPC: H03M3/00
CPC classification number: H03M1/0665 , H03M3/424 , H03M3/464
Abstract: A digital-to analog converter (DAC) of the charge transfer type can be used in a sigma delta modulator for generating N output levels, wherein an output level is defined by a respective amount of charge transferred by the DAC. The DAC has a first capacitor switch unit receiving a reference voltage and a first digital input value to transfer first output charges, at least one second capacitor switch unit receiving the reference voltage and a second digital input value, wherein an output of the second capacitor switch unit is coupled in parallel with an output of the first capacitor switch unit to generate a sum of first and second transferred output charges; and a sequencer controlling switches of the first and second capacitor switch units wherein switching sequences according to individual first and second digital input values are provided for every DAC input value to generate the N output levels.
Abstract translation: 电荷转移型的数模转换器（DAC）可用于Σ-Δ调制器，用于产生N个输出电平，其中输出电平由DAC传输的相应电荷量定义。 DAC具有接收参考电压的第一电容器开关单元和用于传送第一输出电荷的第一数字输入值，接收参考电压的至少一个第二电容开关单元和第二数字输入值，其中第二电容器开关 单元与第一电容器开关单元的输出并联耦合以产生第一和第二传送输出电荷的总和; 以及控制第一和第二电容器开关单元的开关的定序器，其中为每个DAC输入值提供根据各个第一和第二数字输入值的开关序列以产生N个输出电平。
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公开(公告)号：US08742968B2
公开(公告)日：2014-06-03
申请号：US13671903
申请日：2012-11-08
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
CPC classification number: H03M1/10 , G06F13/423 , G06F13/4282 , H03L7/00 , H03L7/06
Abstract: An analog front end (AFE) device has at least one programmable analog-to-digital converter (ADC) and a serial interface switchable to operate in a bidirectional serial interface mode and in a unidirectional two wire serial interface mode, wherein the unidirectional two wire serial interface mode only uses a clock input and a data output signal line, wherein the ADC operates in the unidirectional two wire serial interface mode synchronous with a clock supplied to the clock input.
Abstract translation: 模拟前端（AFE）装置具有至少一个可编程模数转换器（ADC）和可转换成双向串行接口模式和单向双线串行接口模式的串行接口，其中单向两线 串行接口模式仅使用时钟输入和数据输出信号线，其中ADC以提供给时钟输入的时钟同步的单向两线串行接口模式工作。
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公开(公告)号：US20240333301A1
公开(公告)日：2024-10-03
申请号：US18129991
申请日：2023-04-03
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
IPC: H03M3/00
Abstract: A device and method for sigma-delta modulation may include an input signal and a plurality of integrators. The output of the integrators and a data input may be input to an adder, the sum output to be input to a quantizer to generate a quantized output signal. A reset input to the first integrator may be asserted during a first sample of the quantized output signal to reduce the signal discontinuity at the input of the first integrator, which improves the stability of the sigma-delta modulator.
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公开(公告)号：US20210064564A1
公开(公告)日：2021-03-04
申请号：US16998097
申请日：2020-08-20
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix , Yann Johner
Abstract: An apparatus such as a node in a daisy chain of electronic devices includes a serial data input port receive input from an electronic device in the daisy chain. The apparatus includes a serial data output port to send output to another electronic device in the daisy chain. The apparatus includes a chip select input port configured to receive input from a master control unit, and an interface circuit configured to, in a daisy chain streaming mode, and based on a received command and changed edge of a signal on the chip select input port, repeatedly: read data from a data source of the apparatus to yield data, output the data to the serial data output port, and copy other data received at the serial data input port to the serial data output port after the data.
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Patent Agency Ranking
公开(公告)号：US20210064563A1
公开(公告)日：2021-03-04
申请号：US16998050
申请日：2020-08-20
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
Abstract: A node in a daisy chain includes a serial data input port configured to receive input from an electronic device, a serial data output port configured to send output to another electronic device, a chip select input port configured to receive input from a master control unit, a timer, and an interface circuit. The interface circuit may be configured to, in a daisy chain mode, copy data received at the serial data input port to the serial data output port, and upon receipt of a changed edge of a chip select signal on the chip select input port, initiate the timer. The interface circuit may be configured to, upon the completion of a time to be determined by the timer, enter the daisy chain mode.
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27.发明申请公开(公告)号：US20200373939A1
公开(公告)日：2020-11-26
申请号：US16879941
申请日：2020-05-21
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
IPC: H03M3/00
Abstract: An analog to digital converter (ADC) includes voltage and reference input terminals, a buffer circuit, and control logic. The buffer circuit includes input and output terminals and a variable resistor including resistive branches connected in parallel. The control logic is configured to, in a calibration phase, determine a given gain value for which gain error is to be calibrated, determine a set of the resistive branches in the buffer circuit to be used to achieve the given gain value, successively enable a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled, determine an output code resulting after enabling all resistive branches of the set, and, from the output code, determine a gain error of the given gain value. The control logic is further configured to take corrective action based upon the gain error of the given gain value.
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公开(公告)号：US10305452B2
公开(公告)日：2019-05-28
申请号：US16138156
申请日：2018-09-21
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix , Fabien Vaucher
Abstract: A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.
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29.发明授权公开(公告)号：US09584153B2
公开(公告)日：2017-02-28
申请号：US14594388
申请日：2015-01-12
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
CPC classification number: H03M3/33 , H03M1/0641 , H03M1/361 , H03M1/66 , H03M3/424
Abstract: A sigma-delta analog to digital converter (ADC) includes an M-bit digital-to-analog converter (DAC); a loop filter coupled to receive an output from DAC; and a variable level quantizer configured to provide a uniform quantization function by switching between an N-level quantizer function and an N−1 level quantizer function.
Abstract translation: Σ-Δ模数转换器（ADC）包括M位数模转换器（DAC）; 耦合以接收DAC的输出的环路滤波器; 以及可变电平量化器，被配置为通过在N电平量化器功能和N-1电平量化器功能之间切换来提供均匀的量化功能。
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公开(公告)号：US20160028413A1
公开(公告)日：2016-01-28
申请号：US14874729
申请日：2015-10-05
Applicant: MICROCHIP TECHNOLOGY INCORPORATED
Inventor： Vincent Quiquempoix
CPC classification number: H03M3/34 , H03K5/15 , H03M1/00 , H03M1/12 , H03M1/804 , H03M3/30 , H03M3/322 , H03M3/356 , H03M3/422
Abstract: An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference
Abstract translation: 用于开关电容器模拟 - 数字转换器的输入级具有接收输入电压的差分电压输入端，接收斩波参考电压的差分参考电压输入，公共电压连接和差分输出。 一对输入电容器耦合在差分电压输入和差分输出之间，一对参考电容耦合在差分参考电压输入端之间。 开关单元由在第一阶段期间可操作的第一和第二相控制，以将输入电容器的第一端与公共电压连接相连，并将参考电容器的第一端与反相的差分电压基准耦合; 并且在第二阶段期间，将输入电容器的第一端子与差分输入电压连接，并将参考电容器的第一端子与非反相差分电压基准
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