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    APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME
    21.
    发明申请
    APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME 审中-公开

    公开(公告)号：US20180040370A1

    公开(公告)日：2018-02-08

    申请号：US15231518

    申请日：2016-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Russell L. Meyer ,  Agostino Pirovano ,  Andrea Redaelli ,  Lorenzo Fratin ,  Fabio Pellizzer

    IPC: G11C11/56 ,  G11C13/00

    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

    Phase change memory apparatuses
    25.
    发明授权
    Phase change memory apparatuses 有权

    公开(公告)号：US09627440B2

    公开(公告)日：2017-04-18

    申请号：US14285286

    申请日：2014-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo ,  Andrea Redaelli ,  Giorgio Servalli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

    Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.

    Semiconductor Constructions and Memory Arrays
    27.
    发明申请
    Semiconductor Constructions and Memory Arrays 有权
    半导体构造和存储器阵列

    公开(公告)号：US20170025606A1

    公开(公告)日：2017-01-26

    申请号：US15287609

    申请日：2016-10-06

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Cinzia Perrone

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/141 ,  H01L23/481 ,  H01L23/5256 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays.

    Abstract translation: 一些实施例包括具有与上表面的导电互连并且在互连上具有导电结构的半导体结构。 该结构包括沿着上表面的水平的第一部分和在拐角处连接到第一部分的非水平的第二部分。 第二部分具有上边缘。 上边缘相对于互连的上表面偏移，使得上边缘不直接在所述上表面上方。 一些实施例包括存储器阵列。

    Fuses, and methods of forming and using fuses
    30.
    发明授权
    Fuses, and methods of forming and using fuses 有权

    公开(公告)号：US09514905B2

    公开(公告)日：2016-12-06

    申请号：US14629296

    申请日：2015-02-23

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Giorgio Servalli

    IPC: H01H85/04 ,  H01H69/02 ,  H01H37/32 ,  H01H85/11

    CPC classification number: H01H85/06 ,  G11C13/0004 ,  H01H37/32 ,  H01H85/08 ,  H01H85/11 ,  Y10T29/49107

    Abstract: Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.

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