公开(公告)号：US12052862B2

公开(公告)日：2024-07-30

申请号：US17549237

申请日：2021-12-13

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Shyam Surthi

IPC: H01L27/11556 ,  G11C5/02 ,  H01L23/538 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  H01L23/5386 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure, a staircase structure, an etch stop material, and insulative material. The stack structure comprises conductive structures, and air gaps vertically alternating with the conductive structures. The staircase structure is within the stack structure and has steps comprising edges of at least some of the conductive structures of the stack structure. The etch stop material continuously extends over the conductive structures and at least partially defines horizontal boundaries of the air gaps. The insulative material overlies the etch stop material. Additional microelectronic devices, memory devices, electronic systems, and methods are also disclosed.

公开(公告)号：US20230395422A1

公开(公告)日：2023-12-07

申请号：US17863317

申请日：2022-07-12

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  David H. Wells ,  Byeung Chul Kim ,  Richard H. Hill ,  Paolo Tessariol

IPC: H01L21/762 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L21/76232 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519

Abstract: Methods, systems, and devices for selective cavity merging for isolation regions in a memory die are described. For example, formation of material structures of a memory die may include depositing a stack of alternating layers of a first material and a second material over a substrate of the memory die, forming a pattern of cavities through the stack of alternating material layers, and forming voids between layers of the first material based on removing portions of the second material. An electrical isolation region may be formed between portions of the memory die based on depositing a dielectric material in at least some of the cavities and in at least a portion of the voids between the layers of the first material.

公开(公告)号：US20230389311A1

公开(公告)日：2023-11-30

申请号：US17804752

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Xin Lan ,  Byeung Chul Kim ,  Ye Xiang Hong ,  Yun Huang ,  Sok Han Wong

IPC: H01L27/11578 ,  H01L27/11565 ,  H01L29/06

CPC classification number: H01L27/11578 ,  H01L27/11565 ,  H01L29/0649

Abstract: An electronic device includes a stack structure including vertically alternating dielectric materials and conductive materials, the conductive materials including first regions and second regions, and pillars extending vertically through the stack structure, the pillars adjacent to the second regions of the conductive materials. The pillars include cell films adjacent to the second regions, the cell films including a high-k dielectric material, a barrier oxide material, a storage node material, a tunneling material, and a channel material. Segments of each of the high-k dielectric material, the barrier oxide material, and the storage node material are adjacent to the second regions. A length of the segments of high-k dielectric material and a length of the segments of storage node material adjacent to the second regions are greater than a height of the first regions of the conductive materials. Related methods and systems are also disclosed.

公开(公告)号：US20230262981A1

公开(公告)日：2023-08-17

申请号：US18138350

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H10B43/27 ,  G11C16/08 ,  H01L21/02 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/08 ,  H01L21/0214 ,  H10B43/35

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11631697B2

公开(公告)日：2023-04-18

申请号：US17672659

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220173123A1

公开(公告)日：2022-06-02

申请号：US17672659

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210366927A1

公开(公告)日：2021-11-25

申请号：US17393664

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/792 ,  H01L21/02 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US20210057436A1

公开(公告)日：2021-02-25

申请号：US16548267

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L21/02 ,  H01L29/792

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US20200321351A1

公开(公告)日：2020-10-08

申请号：US16374527

申请日：2019-04-03

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  G11C16/08

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230345722A1

公开(公告)日：2023-10-26

申请号：US17726968

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Joshua Wolanyk ,  Richard J. Hill ,  Damir Fazil

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the methods includes forming levels of materials one over another; forming a first opening and a second opening in the levels of materials; forming at least one dielectric material in the first and second openings; forming tiers of materials over the levels of materials and over the dielectric material in the first and second openings; forming a first pillar of a memory cell string, the first pillar extending through the tiers of materials and extending partially into a location of the first opening; and forming a second pillar of a contact structure, the second pillar extending through the tiers of materials and through a location of the second opening.