公开(公告)号：US11557526B2

公开(公告)日：2023-01-17

申请号：US17061435

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Hyunsuk Chun ,  Xiaopeng Qu ,  Chan H. Yoo

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.

公开(公告)号：US20220375902A1

公开(公告)日：2022-11-24

申请号：US17817690

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US20220335000A1

公开(公告)日：2022-10-20

申请号：US17850927

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  George E. Pax ,  Timothy M. Hollis ,  Yogesh Sharma ,  Randon K. Richards ,  Chan H. Yoo ,  Gregory A. King ,  Eric J. Stave

IPC: G06F13/42 ,  G06F11/10 ,  G11C7/10

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

公开(公告)号：US20220208736A1

公开(公告)日：2022-06-30

申请号：US17697141

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532 ,  H01L23/00

Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.

公开(公告)号：US20220149014A1

公开(公告)日：2022-05-12

申请号：US17585392

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

公开(公告)号：US11264332B2

公开(公告)日：2022-03-01

申请号：US16696423

申请日：2019-11-26

Applicant: Micron Technology, Inc.

Inventor： Owen Fay ,  Chan H. Yoo

IPC: H01L23/48 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/14

Abstract: Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.

公开(公告)号：US20210318956A1

公开(公告)日：2021-10-14

申请号：US17356906

申请日：2021-06-24

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G06F12/06 ,  G11C29/12 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US20210272932A1

公开(公告)日：2021-09-02

申请号：US17320116

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Ashok Pachamuthu

IPC: H01L25/065 ,  H01L25/00

Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.

公开(公告)号：US20210202337A1

公开(公告)日：2021-07-01

申请号：US17202542

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Hyunsuk Chun ,  Shams U. Arifeen ,  Chan H. Yoo ,  Tracy N. Tennant

IPC: H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56

Abstract: A semiconductor device having a semiconductor die, a redistribution layer (RDL), and an encapsulant. The RDL layer can be formed on a first surface of the semiconductor die. The encapsulant can enclose a second surface and side surfaces of the semiconductor die. The encapsulant can enclose side portions of the RDL.

公开(公告)号：US20210090969A1

公开(公告)日：2021-03-25

申请号：US17115716

申请日：2020-12-08

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L23/36 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H05K7/20 ,  H01L23/42 ,  H01L25/065

Abstract: Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the first and second devices. The thermally conductive layer and/or the thermal-insulator interposer may be configured to reduce heat transfer between the first and second devices.