公开(公告)号：US10685696B2

公开(公告)日：2020-06-16

申请号：US16176932

申请日：2018-10-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C7/00 ,  G11C11/406 ,  G11C16/34 ,  G11C7/10 ,  G06F11/30 ,  G11C11/4076

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

公开(公告)号：US20190066745A1

公开(公告)日：2019-02-28

申请号：US16137428

申请日：2018-09-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David D. Wilmoth ,  Jason M. Brown

IPC: G11C8/18 ,  G11C11/4063 ,  G11C8/10

CPC classification number: G11C8/18 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C8/10 ,  G11C11/4063 ,  G11C11/4082 ,  G11C11/4093 ,  G11C29/023 ,  G11C29/28 ,  G11C2207/2254

Abstract: Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.

公开(公告)号：US11854618B2

公开(公告)日：2023-12-26

申请号：US17446710

申请日：2021-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniel B. Penney ,  Jason M. Brown

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for determining extremum numerical values. Numerical values may be stored in files of a stack, with each bit of the numerical value stored in a content addressable memory (CAM) cell of the file. Each file may be associated with an accumulator circuit, which provides an accumulator signal. An extremum search operation may be performed where a sequence of comparison bits are compared in a bit-by-bit fashion to each bit of the numerical values. The accumulator circuits each provide an accumulator signal which indicates if the numerical value in the associated file is an extremum value or not. Examples of extremum search operations include finding a maximum of the numerical values and a minimum of the numerical values.

公开(公告)号：US11742008B2

公开(公告)日：2023-08-29

申请号：US17240921

申请日：2021-04-26

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala ,  Todd A. Dauenbaugh

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C7/225

Abstract: A memory device includes a first data driver configured to send according to a first clock signal a first data to a first data port; a second data driver configured to send according to a second clock signal a second data to a second data port, wherein the second clock signal does not match the first clock signal.

公开(公告)号：US20220077112A1

公开(公告)日：2022-03-10

申请号：US17013225

申请日：2020-09-04

Applicant: Micron Technology, Inc

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala

IPC: H01L25/065 ,  G11C13/00 ,  G11C29/00

Abstract: A device may include a first die having a first circuit and a second die having a second circuit. The die may be separated by a material layer. The material layer may include multiple through-silicon vias (TSVs) for electrically coupling the first die to the second die. A first TSV of the TSVs may electrically couple the first circuit to the second circuit and a second TSV of the TSVs may include a redundant TSV that electrically bypasses the first TSV to couple the first circuit to the second circuit if a fault is detected in the first TSV.

公开(公告)号：US20200135263A1

公开(公告)日：2020-04-30

申请号：US16176932

申请日：2018-10-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/406 ,  G11C16/34 ,  G11C11/4076 ,  G11C7/10 ,  G06F11/30

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

公开(公告)号：US20200058344A1

公开(公告)日：2020-02-20

申请号：US16104124

申请日：2018-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vijayakrishna J. Vankayala ,  Jason M. Brown

IPC: G11C11/4076 ,  G11C11/408

Abstract: Apparatuses and methods for a command decoder delay are disclosed. An example apparatus includes a command decoder which may receive memory access command. The command decoder may provide an output command based on the memory access command to a command path at a first time. The command decoder may also provide the output command to a data path at a second time, wherein the second time is delayed relative to the first time.

公开(公告)号：US20200013448A1

公开(公告)日：2020-01-09

申请号：US16557948

申请日：2019-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Harish N. Venkata

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074

Abstract: Apparatuses and methods for providing power for memory refresh operations are described. An example apparatus includes refresh circuits, a power amplifier, a power circuit, and a power control circuits. The refresh circuits are configured to refresh memory cells of a memory bank. The power amplifier is configured to provide power when activated to the refresh circuits. The power provided by the power amplifier has a first voltage. The power circuit is configured to receive a power supply voltage and to provide power when activated to the refresh circuits. The power provided by the power amplifier has a second voltage. The power control circuit is configured to compare the first voltage and the target voltage and to provide an activation signal to control activation of the power circuit having an active duration based at least in part on the comparison.

公开(公告)号：US10438646B1

公开(公告)日：2019-10-08

申请号：US16027158

申请日：2018-07-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Harish N. Venkata

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074

Abstract: Apparatuses and methods for providing power for memory refresh operations are described. An example apparatus includes refresh circuits, a power amplifier, a power circuit, and a power control circuits. The refresh circuits are configured to refresh memory cells of a memory bank. The power amplifier is configured to provide power when activated to the refresh circuits. The power provided by the power amplifier has a first voltage. The power circuit is configured to receive a power supply voltage and to provide power when activated to the refresh circuits. The power provided by the power amplifier has a second voltage. The power control circuit is configured to compare the first voltage and the target voltage and to provide an activation signal to control activation of the power circuit having an active duration based at least in part on the comparison.

公开(公告)号：US10395702B1

公开(公告)日：2019-08-27

申请号：US15977125

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala ,  Todd A. Dauenbaugh

IPC: G11C7/22

Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.