公开(公告)号：US11640397B2

公开(公告)日：2023-05-02

申请号：US17033332

申请日：2020-09-25

Applicant: Micron Technology, Inc.

Inventor： Luca De Santis

IPC: G06F16/2453 ,  G06F16/2455 ,  G06F16/22 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F16/248 ,  G11C8/12 ,  G11C7/10

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array, execute the query, and send only the particular data to the host upon executing the query.

公开(公告)号：US11610637B2

公开(公告)日：2023-03-21

申请号：US17348108

申请日：2021-06-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Apparatus including an array of memory cells, and a controller configured to cause the apparatus to determine a first value indicative of a number of memory cells of a plurality of memory cells that are activated in response to a control gate voltage having a particular voltage level, compare the first value to a plurality of second values, and determine an expected data age of the plurality of memory cells or a plurality of read voltages in response to the comparison of the first value to the plurality of second values.

公开(公告)号：US11416154B2

公开(公告)日：2022-08-16

申请号：US17123472

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US11205481B2

公开(公告)日：2021-12-21

申请号：US17218243

申请日：2021-03-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  H01L27/00 ,  G11C13/06 ,  G11C29/52

Abstract: Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.

公开(公告)号：US11107536B2

公开(公告)日：2021-08-31

申请号：US16916216

申请日：2020-06-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C11/56 ,  G06F11/07 ,  G11C29/02 ,  G11C16/04 ,  G11C29/24

Abstract: Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.

公开(公告)号：US10861551B2

公开(公告)日：2020-12-08

申请号：US16235066

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Umberto Minucci ,  Tommaso Vali ,  Fernanda Irrera ,  Luca De Santis

IPC: G11C16/04 ,  G06N3/063 ,  G06F3/06

Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.

公开(公告)号：US20200335171A1

公开(公告)日：2020-10-22

申请号：US16916216

申请日：2020-06-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C11/56 ,  G06F11/07 ,  G11C29/02

Abstract: Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.

公开(公告)号：US10671479B2

公开(公告)日：2020-06-02

申请号：US16105305

申请日：2018-08-20

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Walter Di Francesco ,  Luca De Santis ,  Giovanni Santin

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/37 ,  G11C29/02 ,  H03M13/29 ,  H03M13/11 ,  G11C29/04 ,  H03M13/45

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

公开(公告)号：US10553289B1

公开(公告)日：2020-02-04

申请号：US16161256

申请日：2018-10-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Marco-Domenico Tiburzi

IPC: G11C16/26 ,  G11C16/34 ,  G11C11/409 ,  G11C7/06 ,  G11C16/28 ,  G11C11/56 ,  G11C16/04 ,  G11C7/14 ,  G11C29/50

Abstract: Methods of operating a memory including applying an intermediate read voltage to a selected access line for a read operation, adding noise to a sensing operation while applying the intermediate read voltage, determining a value indicative of a number of memory cells of a plurality of memory cells connected to the selected access line that are activated in response to applying the intermediate read voltage to the selected access line, and determining an expected data age of the plurality of memory cells in response to the value indicative of the number of memory cells of the plurality of memory cells that are activated in response to applying the intermediate read voltage to the selected access line.

公开(公告)号：US20190325971A1

公开(公告)日：2019-10-24

申请号：US16458384

申请日：2019-07-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C16/04 ,  G11C15/00 ,  G11C15/04

Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.