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公开(公告)号：US11521979B2
公开(公告)日：2022-12-06
申请号：US17112776
申请日：2020-12-04
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa
IPC: G11C11/22 , H01L27/11507 , H01L27/11509 , H01L29/786
Abstract: Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.
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公开(公告)号：US20200381049A1
公开(公告)日：2020-12-03
申请号：US16998834
申请日：2020-08-20
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Adam Johnson
IPC: G11C13/00
Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.
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公开(公告)号：US10783961B2
公开(公告)日：2020-09-22
申请号：US16437997
申请日：2019-06-11
Applicant: Micron Technology, Inc.
Inventor： Wataru Otsuka , Takafumi Kunihiro , Tomohito Tsushima , Makoto Kitagawa , Jun Sumino , D. V. Nirmal Ramaswamy
Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
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公开(公告)号：US20180144792A1
公开(公告)日：2018-05-24
申请号：US15858201
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Wataru Otsuka , Takafumi Kunihiro , Tomohito Tsushima , Makoto Kitagawa , Jun Sumino , D. V. Nirmal Ramaswamy
CPC classification number: G11C13/0002 , G11C13/0009 , G11C13/0011 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/56 , G11C2213/79 , H01L27/2463 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/146
Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
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公开(公告)号：US09911489B2
公开(公告)日：2018-03-06
申请号：US15076451
申请日：2016-03-21
Applicant: Micron Technology, Inc.
Inventor： Wataru Otsuka , Takafumi Kunihiro , Tomohito Tsushima , Makoto Kitagawa , Jun Sumino , D. V. Nirmal Ramaswamy
CPC classification number: G11C13/0002 , G11C13/0011 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/56 , G11C2213/79 , H01L27/2463 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/146
Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
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Patent Agency Ranking
公开(公告)号：US20160225444A1
公开(公告)日：2016-08-04
申请号：US15096135
申请日：2016-04-11
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Kerry Tedrow
IPC: G11C13/00
CPC classification number: G11C13/0064 , G11C7/062 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C2013/0054 , G11C2213/79
Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.
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公开(公告)号：US09123414B2
公开(公告)日：2015-09-01
申请号：US14088046
申请日：2013-11-22
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Yogesh Luthra
CPC classification number: G11C13/0069 , G11C11/16 , G11C13/0011 , G11C13/004 , G11C13/0064 , G11C2013/0054 , G11C2013/0066 , G11C2013/0071 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092 , G11C2213/34 , G11C2213/55 , G11C2213/79
Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.
Abstract translation: 描述了存储器系统和存储器编程方法。 根据一个方面，一种存储器系统包括被配置为向存储器单元提供程序信号以将存储单元从第一存储器状态编程到第二存储器状态的程序电路，检测电路被配置为检测从第一存储器 在将程序信号提供给存储器单元以对存储器单元进行编程期间状态为第二存储器状态，并且其中，程序电路被配置为作为检测的结果改变程序信号，并且将改变的程序信号提供给 存储单元继续将存储单元从第一存储器状态编程到第二存储器状态。
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公开(公告)号：US12073864B2
公开(公告)日：2024-08-27
申请号：US17740528
申请日：2022-05-10
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Daniele Vimercati
CPC classification number: G11C11/2259 , G11C11/221 , G11C11/2273 , G11C11/2275
Abstract: A method of performing a memory cell operation can include maintaining a plate voltage at a first access line of a memory cell during at least a first operation and a second operation of the memory cell. The method can further include charging a second access line to a first voltage greater than zero and greater than a threshold voltage of a selector device of the memory cell during the first operation on the memory cell. The method can further include, subsequent to the first operation, charging the second access line to a second voltage greater than the plate voltage plus the threshold voltage of the selector device to perform the second operation of the memory cell.
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公开(公告)号：US20240249762A1
公开(公告)日：2024-07-25
申请号：US18405792
申请日：2024-01-05
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa
IPC: G11C11/22
CPC classification number: G11C11/2255 , G11C11/221 , G11C11/2273
Abstract: Methods, systems, and devices for mitigating disturbance of digit lines at plate edges are described. Generally, the described techniques relate to disturbance mitigation for one or more memory cells of a sub-array associated with an unselected digit lines located at an edge of the sub-array by including an additional shunt configured to selectively couple the edge digit lines with an associated plate line. For example, a central digit line may be coupled with a respective one of a first set of selection components and a respective one of a second set of selection components, while an edge digit line may be coupled with a respective one of the first set of selection components, a respective one of the second set of selection components, as well as a respective one of a third set of selection components.
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公开(公告)号：US20240212758A1
公开(公告)日：2024-06-27
申请号：US18518051
申请日：2023-11-22
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa
CPC classification number: G11C16/08 , G11C7/08 , G11C16/0433
Abstract: A variety of applications can include a memory device having memory cells that include capacitors as storage units with each capacitor having a plate coupled to a plate line. The memory device can include a plate line driver coupled to specific plate select lines of a set of multiple plate select lines. A plate line driver scheme can include transistors to provide a plate line voltage to a specific plate line and transistors to provide a system reference voltage to the specific plate line, where high state voltages and low state voltages can be applied to specific plate select lines to switch between placing the plate line voltage or the system reference voltage on the specific plate line. Plate select lines and the plate line driver scheme can be arranged to balance the number of plate select lines and device counts for the plate line drivers.
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