公开(公告)号：US10423363B2

公开(公告)日：2019-09-24

申请号：US15470698

申请日：2017-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew A. Prather

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

公开(公告)号：US20190107975A1

公开(公告)日：2019-04-11

申请号：US16212572

申请日：2018-12-06

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Frank F. Ross

IPC: G06F3/06

Abstract: A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference.

公开(公告)号：US20190107974A1

公开(公告)日：2019-04-11

申请号：US16212565

申请日：2018-12-06

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather

IPC: G06F3/06

Abstract: A memory device is provided. The memory device includes a memory array, operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device, and delay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command. The one or more bits indicate a duration by which to delay the performance of the memory operation.

公开(公告)号：US20150046631A1

公开(公告)日：2015-02-12

申请号：US13965008

申请日：2013-08-12

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather

IPC: G06F3/06

CPC classification number: G06F3/0685 ,  G06F3/061 ,  G06F3/0658 ,  G06F12/0246 ,  G06F13/1668 ,  G06F2212/205

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Abstract translation: 描述了用于配置用于混合存储器模块的存储器的I / O的装置，混合存储器模块，存储器和方法。 示例性设备包括非易失性存储器，耦合到非易失性存储器的控制电路和耦合到控制电路的易失性存储器。 易失性存储器被配置为使得能够与总线通信的I / O的第一子集，并且使能与控制电路通信的I / O的第二子集，其中控制电路被配置为在易失性存储器和 非易失性存储器。

公开(公告)号：US12135600B2

公开(公告)日：2024-11-05

申请号：US17479922

申请日：2021-09-20

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F1/32 ,  G06F1/3234 ,  G06F3/06 ,  G11C5/14

Abstract: The present disclosure includes apparatuses and methods related to power management in memory. Memory devices with multiple input/output ports may have the ports separately managed to transfer data from the various to a host or other components of the module based on certain power management signaling or constraints. For example, a memory device with multiple ports may be managed to transfer data to a host from one set of ports in response to power management (or other) signaling, and the device may be managed to transfer other data to another memory device in response to different power management (or other signaling). Power management may be done onboard a memory module with or without direction from a host. Power management may be performed by a dedicated integrated circuit. Data may be transferred from or between different classes of memory devices, using different ports, based on power management, e.g., criteria.

公开(公告)号：US20240290409A1

公开(公告)日：2024-08-29

申请号：US18444446

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather

IPC: G11C29/02 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C29/027 ,  G11C17/16 ,  G11C17/18

Abstract: Memory devices may be assigned enumeration values that uniquely identify the memory devices in a multi-memory device system. In some examples, the enumeration value is assigned by programming one or more fuses in the memory device. In some examples, a post-package repair operation may be used to program the fuses.

公开(公告)号：US11942404B2

公开(公告)日：2024-03-26

申请号：US17411879

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Scott R. Cyr ,  Stephen F. Moxham ,  Matthew A. Prather ,  Scott Smith

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/105 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16235 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/14361

Abstract: Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

公开(公告)号：US20230367709A1

公开(公告)日：2023-11-16

申请号：US18144655

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Scott E. Smith ,  Matthew A. Prather ,  Erik V. Pohlmann

IPC: G06F12/06 ,  G06F11/07

CPC classification number: G06F12/06 ,  G06F11/0727 ,  G06F2212/1032

Abstract: Methods, systems, and devices for write command timing enhancement are described. A host device may transmit (e.g., issue), to a memory device, an activation command and an associated write command according to a delay that is different (e.g., shorter) than a row access to column access delay associated with read commands. In some examples, the delay between the activation command and the associated write command may be a function of the row access to column access delay associated with read commands and one or more additional parameters, such as a timing constraint or a speed parameter of the memory device.

公开(公告)号：US11783882B2

公开(公告)日：2023-10-10

申请号：US17379422

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Thomas H. Kinsley

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10 ,  G11C11/407

CPC classification number: G11C11/40611 ,  G11C7/1072 ,  G11C11/407

Abstract: Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.

公开(公告)号：US20230205712A1

公开(公告)日：2023-06-29

申请号：US18084452

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather

IPC: G06F13/16 ,  G06F13/40 ,  G06F11/07

CPC classification number: G06F13/1694 ,  G06F13/409 ,  G06F13/1689 ,  G06F11/0787

Abstract: A memory module is provided, comprising a connector and a plurality of memory devices. Each memory device includes a memory array and a plurality of data connections, wherein a first subset of the plurality of data connections are configured to communicate data with a first portion of the memory array, and a second subset of the plurality of data connections are configured to communicate data with a second portion of the memory array. The first subset of the plurality of data connections of each of the plurality of memory devices are connected in parallel to first external contacts of the connector in a first addressable pseudo-channel, and the second subset of the plurality of data connections of each of the plurality of memory devices are connected in parallel to second external contacts of the connector in a second addressable pseudo-channel.