公开(公告)号：US20240234311A1

公开(公告)日：2024-07-11

申请号：US18610267

申请日：2024-03-20

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Haitao Liu ,  Vladimir Mikhalev

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L23/528 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827 ,  H10B10/12

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

公开(公告)号：US20240154033A1

公开(公告)日：2024-05-09

申请号：US18406827

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7831 ,  H01L29/1033

Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.

公开(公告)号：US20240107754A1

公开(公告)日：2024-03-28

申请号：US18533291

申请日：2023-12-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith

IPC: H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Method of forming an isolation structure might include forming a first conductive region in a first section of a semiconductor material, forming a first trench in a second section of the semiconductor material adjacent a first side of the first section of the semiconductor material and forming a second trench in a third section of the semiconductor material adjacent a second side of the first section of the semiconductor material, extending the first and second trenches to a depth below the first conductive region and removing a portion of the first section of the semiconductor material overlying the first conductive region, forming second and third conductive regions in the semiconductor material below bottoms of the first and second trenches, respectively, and forming a dielectric material overlying the first conductive region and filling the first and second trenches.

公开(公告)号：US11889687B2

公开(公告)日：2024-01-30

申请号：US17508353

申请日：2021-10-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith

IPC: H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Integrated circuit structures might include a semiconductor material, a first active area in the semiconductor material, a second active area in the semiconductor material, and an isolation structure comprising a dielectric material deposited in a trench formed in the semiconductor material between the first active area and the second active area. The isolation structure might further include a first edge portion extending below a surface of the semiconductor material to a first depth, a second edge portion extending below the surface of the semiconductor material to the first depth, and an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor material to a second depth, less than the first depth.

公开(公告)号：US20230050443A1

公开(公告)日：2023-02-16

申请号：US17401239

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp

IPC: G11C16/08 ,  G11C16/04 ,  H01L29/10 ,  H01L29/78

Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

公开(公告)号：US11430887B2

公开(公告)日：2022-08-30

申请号：US17095475

申请日：2020-11-11

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/78 ,  H01L29/10

Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.

公开(公告)号：US20210407989A1

公开(公告)日：2021-12-30

申请号：US17473285

申请日：2021-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/06 ,  H01L27/11526 ,  H01L27/11573 ,  G11C16/22 ,  H01L21/28

Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

公开(公告)号：US11158367B1

公开(公告)日：2021-10-26

申请号：US16846120

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： Kenneth W. Marr ,  Michael A. Smith

IPC: G11C7/24 ,  G11C11/4078 ,  G11C16/22 ,  G11C16/04 ,  G11C8/20 ,  G11C11/22 ,  G11C11/16

Abstract: Memory devices are disclosed. A memory device may include a source (SRC) plate configured to couple to a number of memory cells. The memory device may also include a resistor coupled between the source plate and a node. Further, the memory device may include at least one transistor coupled between the source plate and the ground voltage, wherein a gate of the at least one transistor is coupled to the node. The transistor may be configured to couple the SRC plate to the ground voltage during a processing stage. The transistor may further be configured to isolate the SRC plate from the ground voltage during an operation stage. Methods and electronic systems are also disclosed.

公开(公告)号：US20210074864A1

公开(公告)日：2021-03-11

申请号：US17087842

申请日：2020-11-03

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/94 ,  H01L29/49 ,  H01L21/28 ,  G11C16/30 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/66

Abstract: A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.

公开(公告)号：US20210035997A1

公开(公告)日：2021-02-04

申请号：US16527552

申请日：2019-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith

IPC: H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11529

Abstract: Integrated circuits, and integrated circuit devices, might include is semiconductor, a first active area in the semiconductor, a second active area in the semiconductor, and an isolation structure in the semiconductor between the first active area and the second active area. The isolation structure might include a first edge portion extending below a surface of the semiconductor to a first depth, a second edge portion extending below the surface of the semiconductor to the first depth, and an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor to a second depth, less than the first depth.