公开(公告)号：US20160005447A1

公开(公告)日：2016-01-07

申请号：US14854418

申请日：2015-09-15

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C8/10 ,  G11C7/06

CPC classification number: G11C8/10 ,  G06F9/30 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/0888 ,  G06F13/40 ,  G06F2212/7202 ,  G11C7/06 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/419 ,  G11C15/04 ,  G11C2207/2245 ,  Y02D10/13

Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

公开(公告)号：US20150131390A1

公开(公告)日：2015-05-14

申请号：US14603850

申请日：2015-01-23

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

公开(公告)号：US20150063052A1

公开(公告)日：2015-03-05

申请号：US14015732

申请日：2013-08-30

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G06F9/30 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/0888 ,  G06F13/40 ,  G06F2212/7202 ,  G11C7/06 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/419 ,  G11C15/04 ,  G11C2207/2245 ,  Y02D10/13

Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

Abstract translation: 本公开的示例提供用于访问存储器阵列地址空间的设备和方法。 一种示例性存储器阵列，其包括第一地址空间，该第一地址空间包括耦合到第一数量的选择线和多条感测线的存储器单元，以及包括耦合到第二数量的选择线的存储器单元和感测线的数量的第二地址空间 。 第一地址空间相对于第二地址空间可独立地寻址。

公开(公告)号：US20150029798A1

公开(公告)日：2015-01-29

申请号：US13952054

申请日：2013-07-26

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Abstract translation: 本公开包括与使用感测电路执行比较和/或报告操作相关的装置和方法。 示例性方法可以包括将存储器阵列的输入/输出（IO）线充电到电压。 该方法可以包括确定存储在存储器阵列中的数据是否与比较值相匹配。 确定存储的数据是否与比较值匹配可以包括激活存储器阵列的多个访问线。 该确定可以包括感测耦合到接入线路数量的多个存储器单元。 该确定可以包括检测IO线的电压是否响应于对应于存储器单元的数量的所选择的解码线的激活而改变。

公开(公告)号：US20250138781A1

公开(公告)日：2025-05-01

申请号：US18787854

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Xinyu Wu ,  Peter L. Brown ,  Troy A. Manning

IPC: G06F7/523 ,  G06F7/50

Abstract: A processing unit can include an activation function unit. Data can be received at a plurality of registers of a processing unit of a memory sub-system. The data can be received at a multiply-accumulate (MAC) unit coupled to the plurality of registers. The first plurality of operations can be performed at the MAC unit to generate a first output. The first output can be provided to the activation function unit. The first output can be provided from the AFU to the plurality of registers utilizing a bus or a signal line that couples the plurality of registers to the AFU.

公开(公告)号：US20230333744A1

公开(公告)日：2023-10-19

申请号：US18211356

申请日：2023-06-19

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner

IPC: G11C8/12 ,  G11C7/10 ,  G06F15/78 ,  G06F3/06 ,  G11C29/28

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0683 ,  G06F15/7821 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12 ,  G11C29/28 ,  G11C2029/2602

Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

公开(公告)号：US11726791B2

公开(公告)日：2023-08-15

申请号：US17743062

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Richard C. Murphy ,  Troy A. Manning ,  Dean A. Klein

IPC: G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G06F9/3877 ,  G06F15/7821 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4087 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：US20230033704A1

公开(公告)日：2023-02-02

申请号：US17885143

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Jonathan D. Harms ,  Troy D. Larsen ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F9/4401 ,  G06F9/38 ,  G06F12/0868 ,  G06F13/16 ,  G06F12/1045

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

公开(公告)号：US20220343969A1

公开(公告)日：2022-10-27

申请号：US17859992

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Glen E. Hush

IPC: G11C11/4091 ,  G11C11/4097 ,  H03K19/20 ,  H03K19/0948 ,  G11C7/10

Abstract: The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.

公开(公告)号：US11422826B2

公开(公告)日：2022-08-23

申请号：US16878226

申请日：2020-05-19

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Jonathan D. Harms ,  Troy D. Larsen ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F9/4401 ,  G06F9/38 ,  G06F12/0868 ,  G06F13/16 ,  G06F12/1045

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.