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公开(公告)号：US20220188040A1
公开(公告)日：2022-06-16
申请号：US17685102
申请日：2022-03-02
发明人： Gianni Stephen Alsasua , Harish Reddy Singidi , Peter Sean Feeley , Ashutosh Malshe , Renato Padilla, JR. , Kishore Kumar Muchherla , Sampath Ratnam
摘要： Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
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公开(公告)号：US11269553B2
公开(公告)日：2022-03-08
申请号：US16878304
申请日：2020-05-19
发明人： Gianni Stephen Alsasua , Harish Reddy Singidi , Peter Sean Feeley , Ashutosh Malshe , Renato Padilla, Jr. , Kishore Kumar Muchherla , Sampath Ratnam
摘要： Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
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公开(公告)号：US20210390014A1
公开(公告)日：2021-12-16
申请号：US17458224
申请日：2021-08-26
发明人： Chun Sum Yeung , Falgun G. Trivedi , Harish Reddy Singidi , Xiangang Luo , Preston Allen Thomson , Ting Luo , Jianmin Huang
IPC分类号： G06F11/10 , G06F12/0882 , G06F11/07 , G06F12/02
摘要： A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20210257031A1
公开(公告)日：2021-08-19
申请号：US17313249
申请日：2021-05-06
发明人： Ashutosh Malshe , Kishore Kumar Muchherla , Harish Reddy Singidi , Peter Sean Feeley , Sampath Ratnam , Kulachet Tanpairoj , Ting Luo
摘要： Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
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公开(公告)号：US11056156B2
公开(公告)日：2021-07-06
申请号：US16749481
申请日：2020-01-22
发明人： Kishore Kumar Muchherla , Ashutosh Malshe , Harish Reddy Singidi , Gianni Stephen Alsasua , Gary F. Besinga , Sampath Ratnam , Peter Sean Feeley
摘要： A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US11043278B2
公开(公告)日：2021-06-22
申请号：US17017291
申请日：2020-09-10
发明人： Ashutosh Malshe , Kishore Kumar Muchherla , Harish Reddy Singidi , Peter Sean Feeley , Sampath Ratnam , Kulachet Tanpairoj , Ting Luo
IPC分类号： G11C7/00 , G11C16/26 , G11C16/04 , G11C16/28 , G11C16/34 , G11C29/02 , G11C16/24 , G11C16/08
摘要： Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
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公开(公告)号：US20210125675A1
公开(公告)日：2021-04-29
申请号：US17141964
申请日：2021-01-05
摘要： A variety of applications can include systems and/or methods of optimizing results from scanning a memory device, where the memory device has stacked multiple reliability specifications. Information about a block of multiple blocks of a memory device can be logged, where the information is associated with a combination of reliability specifications. A refresh of the block can be triggered based on exceeding a threshold condition for the combination of reliability specifications. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20200335172A1
公开(公告)日：2020-10-22
申请号：US16920154
申请日：2020-07-02
发明人： Harish Reddy Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Micheal G. Miller
摘要： Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
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公开(公告)号：US20200278814A1
公开(公告)日：2020-09-03
申请号：US16878304
申请日：2020-05-19
发明人： Gianni Stephen Alsasua , Harish Reddy Singidi , Peter Sean Feeley , Ashutosh Malshe , Renato Padilla, JR. , Kishore Kumar Muchherla , Sampath Ratnam
摘要： Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
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公开(公告)号：US10755792B2
公开(公告)日：2020-08-25
申请号：US16448502
申请日：2019-06-21
发明人： Harish Reddy Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Michael G. Miller
摘要： Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
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