公开(公告)号：US06541866B1

公开(公告)日：2003-04-01

申请号：US09778113

申请日：2001-02-07

申请人： Jacques J. Bertrand ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  George J. Kluth

发明人： Jacques J. Bertrand ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  George J. Kluth

IPC分类号： H01L2348

CPC分类号： H01L21/28052 ,  H01L29/4941

摘要： Nickel silicidation of a gate electrode is controlled using a cobalt barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of cobalt thereon and an upper polycrystalline silicon layer on the cobalt layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel suicide and a cobalt silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.

摘要翻译： 使用钴阻挡层控制栅电极的镍硅化。 实施例包括形成包括下多晶硅层，钴层上的钴层和钴层上的上多晶硅层的栅电极结构，沉积镍层和硅化物，由此将上多晶硅层转化为硅化镍， 形成防止镍与下部多晶硅层反应的硅化钴阻挡层。

公开(公告)号：US06441490B1

公开(公告)日：2002-08-27

申请号：US09774849

申请日：2001-01-30

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L2940

CPC分类号： H01L23/5329 ,  H01L21/76807 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.

摘要翻译： 提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。 器件电介质层上的沟道电介质层具有通道开口和填充沟道开口的导体芯。 在通道电介质层上形成通孔停止层，使氢浓度低于15原子％，并且在通孔停止层上方形成通孔电介质层，并具有通孔。 通孔电介质层上的第二通道介电层具有第二通道开口。 填充第二通道开口和通孔开口的第二导体芯连接到半导体器件。

公开(公告)号：US06989604B1

公开(公告)日：2006-01-24

申请号：US10672103

申请日：2003-09-26

申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

IPC分类号： H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76876 ,  H01L2221/1089

摘要： An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

摘要翻译： 一种在其上具有基板和半导体器件的集成电路。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

公开(公告)号：US06830998B1

公开(公告)日：2004-12-14

申请号：US10462667

申请日：2003-06-17

申请人： James Pan ,  Paul Besser ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  Jinsong Yin

发明人： James Pan ,  Paul Besser ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  Jinsong Yin

IPC分类号： H01L213205

CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545

摘要： Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.

摘要翻译： 在更换金属栅极处理期间由于等离子体损坏引起的栅极介质劣化被固化并且通过在去除多晶硅栅极之后处理栅极电介质来防止进一步的等离子体劣化。 实施例包括在金属沉积之前的金属沉积和CMP之后的低温真空退火，在氧气和氩气中的退火，在金属沉积之前的臭氧或形成气体，或者在金属沉积之前的硅烷或乙硅烷中的热浸渍。

公开(公告)号：US06723635B1

公开(公告)日：2004-04-20

申请号：US10115245

申请日：2002-04-04

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Steven C. Avanzino ,  John E. Sanchez, Jr. ,  Suzette K. Pangrle

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Steven C. Avanzino ,  John E. Sanchez, Jr. ,  Suzette K. Pangrle

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76807

摘要： Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.

摘要翻译： 通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。 实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用 铜。

公开(公告)号：US06713392B1

公开(公告)日：2004-03-30

申请号：US10234238

申请日：2002-09-05

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L29/6656

摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen oxide plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

摘要翻译： 通过用氮氧化物等离子体处理氮化硅侧壁间隔物的暴露表面以产生具有减少的游离硅的表面区域，防止栅极电极上的硅化镍层与沿着氮化硅侧壁间隔物的源极/漏极区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

公开(公告)号：US06555461B1

公开(公告)日：2003-04-29

申请号：US09884059

申请日：2001-06-20

申请人： Christy Mei-Chu Woo ,  Suzette K. Pangrle ,  Minh Van Ngo

发明人： Christy Mei-Chu Woo ,  Suzette K. Pangrle ,  Minh Van Ngo

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate.

摘要翻译： 用于形成金属互连结构的方法在电介质层的图案化开口内提供诸如氮化物之类的阻挡材料的共形层。 在将开口蚀刻到电介质层上之后，阻挡材料沉积，停止在扩散阻挡层上。 诸如钽的金属阻挡材料的第一层被共形沉积在阻挡材料上。 执行定向蚀刻，其去除水平氮化物和钽，留下图案化开口的侧壁上的氮化物和钽。 阻挡材料在覆盖导电材料的扩散阻挡层的蚀刻期间以及在随后的溅射蚀刻清洁期间防止介电层从导电材料（例如铜）中的污染。 薄的第二金属层被共形沉积，并且在开口的侧壁上形成合适的阻挡层，同时在第二金属层和下面的基底之间提供低的接触电阻。

公开(公告)号：US06455422B1

公开(公告)日：2002-09-24

申请号：US09705444

申请日：2000-11-02

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76883

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer of titanium, tantalum, tungsten, or a nitride of the aforegoing is deposited to line the opening, and a copper or copper alloy conductor core is deposited to fill the channel opening over the barrier layer. After planarization of the conductor core and the barrier layer, an ammonia, nitrogen hydride, or hydrogen plasma treatment is performed below 300° C. to reduce the residual oxide on the conductor core material. The plasma treatment is followed by the deposition of a silicon nitride capping layer performed below 300° C. After the reducing and deposition process, a densification process is performed between 380° C. and 420° C. to density the capping layer to enhance the quality of the silicon nitride layer.

摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 在半导体基板上形成器件电介质层，在器件电介质层上形成的沟道电介质层形成有开口部。 沉积钛，钽，钨或前述氮化物的阻挡层以对开口进行排列，并且沉积铜或铜合金导体芯以填充阻挡层上的通道开口。 在导体芯和阻挡层平坦化之后，在300℃以下进行氨，氮化氢或氢等离子体处理以减少导体芯材上的残余氧化物。 等离子体处理之后，在300℃以下进行氮化硅覆盖层的沉积。在还原和沉积工艺之后，在380℃和420℃之间进行致密化过程以密封覆盖层以增强 氮化硅层的质量。

公开(公告)号：US06836017B2

公开(公告)日：2004-12-28

申请号：US10759170

申请日：2004-01-20

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Steven C. Avanzino ,  John E. Sanchez, Jr. ,  Suzette K. Pangrle

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Steven C. Avanzino ,  John E. Sanchez, Jr. ,  Suzette K. Pangrle

IPC分类号： H01L2348

CPC分类号： H01L21/76831 ,  H01L21/76807

摘要： Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.

摘要翻译： 通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。 实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用 铜。

公开(公告)号：US06724051B1

公开(公告)日：2004-04-20

申请号：US09679877

申请日：2000-10-05

申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  George Jonathan Kluth

发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  George Jonathan Kluth

IPC分类号： H01L2976

CPC分类号： H01L29/665 ,  H01L29/4983 ,  Y10S257/90

摘要： A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide, first and second sidewall spacers, and nickel silicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first and second sidewall spacers are respectively disposed adjacent the first and second sidewalls. The first and second sidewall spacers are formed from a low-K spacer material that is substantially non-reactive with nickel, for example, SiHC, hydrogen silsesquioxane and methyl silsesquioxane. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： MOSFET半导体器件包括衬底，栅电极，栅极氧化物，第一和第二侧壁间隔物以及镍硅化物层。 栅极氧化物设置在栅极电极和衬底之间，并且衬底包括源极/漏极区域。 栅电极具有第一和第二相对的侧壁，并且第一和第二侧壁间隔件分别设置成与第一和第二侧壁相邻。 第一和第二侧壁间隔物由基本上不与镍反应的低K间隔材料形成，例如SiHC，氢倍半硅氧烷和甲基倍半硅氧烷。 硅化镍层设置在源/漏区和栅电极上。 还公开了制造半导体器件的方法。