公开(公告)号：US20110065214A1

公开(公告)日：2011-03-17

申请号：US12561618

申请日：2009-09-17

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer

IPC分类号： H01L21/50 ,  G06F17/00

CPC分类号： H01L24/94 ,  H01L22/14 ,  H01L22/20 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2225/06596 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

摘要： A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.

摘要翻译： 形成三维（3D）模具的过程。 针对通过（良好的模具）或失败（坏模具）预定测试标准的模具测试多个晶片。 两个测试的晶片彼此靠近放置。 以这样的方式对晶片进行对准，以便使两个晶片之间对准的良好裸片的数量最大化。 然后将两个晶片结合在一起并切成多个粘结好的模具的各个叠层。

公开(公告)号：US07939369B2

公开(公告)日：2011-05-10

申请号：US12465839

申请日：2009-05-14

申请人： Mukta G. Farooq ,  Subramanian S. Iyer

发明人： Mukta G. Farooq ,  Subramanian S. Iyer

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/94 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/16 ,  H01L24/28 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80801 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metallic layers of each of the semiconductor structures face each other. The metallic layers of each of the semiconductor structures are in contact with and bonded to each other by a metal to metal bond wherein the bonded metallic layers form an electrically isolated layer.

摘要翻译： 制作3D集成电路和3D集成电路结构的方法。 连接到第二半导体结构的第一半导体结构。 每个半导体结构包括半导体晶片，半导体晶片上的线的前端（FEOL）布线，FEOL布线上的线的后端（BEOL）布线，BEOL布线上的绝缘体层和金属层 绝缘体层。 第一半导体结构与第二半导体结构对准，使得每个半导体结构的金属层彼此面对。 每个半导体结构的金属层通过金属 - 金属键彼此接触并彼此结合，其中结合的金属层形成电隔离层。

公开(公告)号：US08372725B2

公开(公告)日：2013-02-12

申请号：US12710553

申请日：2010-02-23

申请人： Robert Hannon ,  Subramanian S. Iyer ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Kevin R. Winstel

发明人： Robert Hannon ,  Subramanian S. Iyer ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Kevin R. Winstel

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76251 ,  H01L21/84 ,  H01L29/66181

摘要： Structures and methods are provided for forming pre-fabricated deep trench capacitors for SOI substrates. The method includes forming a trench in a substrate and forming a dielectric material in the trench. The method further includes depositing a conductive material over the dielectric material in the trench and forming an insulator layer over the conductive material and the substrate.

摘要翻译： 提供了用于形成用于SOI衬底的预制深沟槽电容器的结构和方法。 该方法包括在衬底中形成沟槽并在沟槽中形成电介质材料。 该方法还包括在沟槽中的电介质材料上沉积导电材料，并在导电材料和衬底之上形成绝缘体层。

公开(公告)号：US06353246B1

公开(公告)日：2002-03-05

申请号：US09197693

申请日：1998-11-23

申请人： Robert Hannon ,  Subramanian S. Iyer ,  Scott R. Stiffler ,  Kevin R. Winstel

发明人： Robert Hannon ,  Subramanian S. Iyer ,  Scott R. Stiffler ,  Kevin R. Winstel

IPC分类号： H01L2701

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/12

摘要： A semiconductor device structure including a substrate including at least one silicon-on-insulator substrate region and at least one non-silicon-on-insulator region. The at least one silicon-on-insulator region and at least one non-silicon-on-insulator region are formed in a pattern in the substrate. At least one trench is arranged in the vicinity of at least at a portion of a boundary between a silicon-on-insulator substrate region and the non-silicon-on-insulator substrate region. The at least one trench is arranged in at least one of the silicon-on-insulator region and the non-silicon-on-insulator region.

摘要翻译： 一种半导体器件结构，包括包括至少一个绝缘体上硅衬底区域和至少一个绝缘体上非绝缘体区域的衬底。 至少一个绝缘体上的区域和至少一个绝缘体上的非绝缘体区域以衬底的形式形成。 至少在绝缘体上硅衬底区域和非硅绝缘体衬底区域之间的边界的至少一部分附近布置至少一个沟槽。 所述至少一个沟槽布置在绝缘体上硅区域和绝缘体上非绝缘体区域中的至少一个中。

公开(公告)号：US06261876B1

公开(公告)日：2001-07-17

申请号：US09434191

申请日：1999-11-04

申请人： Scott W. Crowder ,  Robert Hannon ,  Subramanian S. Iyer

发明人： Scott W. Crowder ,  Robert Hannon ,  Subramanian S. Iyer

IPC分类号： H01L2100

CPC分类号： H01L21/76243

摘要： A process for creating a substrate including bulk silicon regions and semiconductor-on-insulator regions. Regions of a surface of a bulk silicon substrate are recessed above regions where it is desired to create buried oxide regions in the substrate. Implant mask regions are formed on the surface of the substrate over regions where it is not desired to create buried oxide regions. Buried oxide regions are formed in the substrate under the recessed regions in the substrate. The implant mask regions are removed, leaving bulk silicon regions between the buried oxide regions.

摘要翻译： 一种用于产生包括体硅区域和绝缘体上半导体区域的衬底的工艺。 体硅衬底的表面的区域在需要在衬底中产生掩埋氧化物区域的区域上凹进。 在不需要产生掩埋氧化物区域的区域上，在衬底的表面上形成植入掩模区域。 埋设的氧化物区域形成在衬底中的衬底中的凹陷区域内。 去除注入掩模区域，留下掩埋氧化物区域之间的体硅区域。

公开(公告)号：US6096580A

公开(公告)日：2000-08-01

申请号：US405331

申请日：1999-09-24

申请人： S. Sundar Kumar Iyer ,  Liang-Kai Han ,  Robert Hannon ,  Subramanian S. Iyer ,  Mukesh V. Khare

发明人： S. Sundar Kumar Iyer ,  Liang-Kai Han ,  Robert Hannon ,  Subramanian S. Iyer ,  Mukesh V. Khare

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.

摘要翻译： 描述了由MOSFET（或MOS）或深沟槽（DT）电容器结构形成的低编程电压反熔丝。 降低编程电压可以通过将一定剂量的重离子（如铟）直接注入到基底上的电介质或间接通过多晶硅层来实现。 通过在处理期间通过适当的布局掩模强调器件的有源区域和栅极区域的角，也可以在MOSFET / MOS电容器反熔丝上降低编程电压。 在制造抗熔丝的同时，也应避免硅有源区四舍五入步骤，以减少编程电压。 在DT电容器中，降低编程电压可以通过直接或通过沉积在其上的多晶硅的保形层或在第一非晶硅凹槽步骤之后的重离子注入DT反熔丝的节点电介质来实现， DT电容器。

公开(公告)号：US09184129B2

公开(公告)日：2015-11-10

申请号：US13004129

申请日：2011-01-11

申请人： Byeongju Park ,  Subramanian S. Iyer ,  Chandrasekharan Kothandaraman

发明人： Byeongju Park ,  Subramanian S. Iyer ,  Chandrasekharan Kothandaraman

IPC分类号： H01L23/525 ,  H01L27/112 ,  G11C17/16

CPC分类号： H01L23/5252 ,  G11C17/165 ,  G11C2229/763 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/928 ,  H01L2924/00

摘要： The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

摘要翻译： 本发明提供了具有集成加热元件的反熔丝结构及其编程方法，反熔丝结构包括第一和第二导体以及形成在导体之间的介电层，其中一个或两个导体用作传统的反熔丝导体和 作为用于在编程期间直接加热反熔丝介电层的加热元件。

公开(公告)号：US08629017B2

公开(公告)日：2014-01-14

申请号：US13417900

申请日：2012-03-12

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US08590010B2

公开(公告)日：2013-11-19

申请号：US13302314

申请日：2011-11-22

申请人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

发明人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

IPC分类号： H03M13/05

CPC分类号： G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

摘要： A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

摘要翻译： 随机内在芯片ID生成采用保留失败签名。 使用测试设置生成第1和第2个ID，第一个设置比第二个设置的限制要大于第二个设置，在包含第二个ID位串的第一个ID位字符串中创建更多的故障。 保留暂停时间控制由BIST引擎调整的保留失败次数，其中失败号码满足预定的失败目标。 验证确认第一ID是否包含第二ID位字符串，该ID是用于认证的ID。 认证由具有中间条件的第三ID启用，使得第一ID包括第三ID位串，第三ID包括第二ID位串。 中间条件包括用于消除第1和第2 ID边界附近的位不稳定性问题的保护带。 在每次ID读取操作中改变中间条件，导致更安全的识别。

公开(公告)号：US20130133031A1

公开(公告)日：2013-05-23

申请号：US13302314

申请日：2011-11-22

申请人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

发明人： Daniel J. Fainstein ,  Alberto Cestero ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Norman W. Robson ,  Sami Rosenblatt

IPC分类号： G06F21/00

CPC分类号： G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

摘要： A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

摘要翻译： 随机内在芯片ID生成采用保留失败签名。 使用测试设置生成第1和第2个ID，第一个设置比第二个设置的限制要大于第二个设置，在包含第二个ID位串的第一个ID位字符串中创建更多的故障。 保留暂停时间控制由BIST引擎调整的保留失败次数，其中失败号码满足预定的失败目标。 验证确认第一ID是否包含第二ID位字符串，该ID是用于认证的ID。 认证由具有中间条件的第三ID启用，使得第一ID包括第三ID位串，第三ID包括第二ID位串。 中间条件包括用于消除第1和第2 ID边界附近的位不稳定性问题的保护带。 在每次ID读取操作中改变中间条件，导致更安全的识别。