公开(公告)号：US20230099467A1

公开(公告)日：2023-03-30

申请号：US17947446

申请日：2022-09-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takumi ENDOU ,  Sho WATANABE ,  Akito MORI ,  Masahiro WAKASHIMA

IPC: H01G4/12 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes dielectric layers made of a ceramic material and internal electrode layers laminated therein. The internal electrode layers each include dielectric columns provided therein. A solid solution layer in which S is solidly dissolved is provided at an interface between each of the dielectric columns and each of the internal electrode layers.

公开(公告)号：US20220148812A1

公开(公告)日：2022-05-12

申请号：US17495853

申请日：2021-10-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yu TSUTSUI ,  Yuta KUROSU ,  Daiki FUKUNAGA ,  Yuta SAITO ,  Masahiro WAKASHIMA

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008 ,  H01G13/00 ,  C04B35/468

Abstract: A method of manufacturing a multilayer ceramic capacitor includes printing an internal electrode pattern on a dielectric layer, forming a dielectric pattern in a region other than a region in which the internal electrode pattern is printed, laminating dielectric layers to form a multilayer body, exposing the internal electrode pattern and the dielectric pattern from a side surface of the multilayer body, removing at least a portion of the exposed dielectric pattern, and forming a dielectric gap layer on the side surface.

公开(公告)号：US20220102079A1

公开(公告)日：2022-03-31

申请号：US17487385

申请日：2021-09-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers, the external electrode layers each further including a base electrode layer including a first region, a second region, and a third region divided therein, in order from the multilayer body. The first region includes a metal included in the internal electrode layers in a higher amount than the second region and the third region, the second region includes glass in a higher amount than the first region and the third region, and the third region includes copper in a higher amount than the first region and the second region.

公开(公告)号：US20210350983A1

公开(公告)日：2021-11-11

申请号：US17368909

申请日：2021-07-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki FUKUNAGA ,  Hideaki TANAKA ,  Masahiro WAKASHIMA ,  Daisuke HAMADA ,  Hironori TSUTSUMI ,  Satoshi MAENO ,  Ryota ASO ,  Koji MORIYAMA ,  Akihiro TSURU

IPC: H01G4/12 ,  H01G4/012 ,  H01G4/008 ,  H01G4/232 ,  H01G4/224

Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.

公开(公告)号：US20210202179A1

公开(公告)日：2021-07-01

申请号：US17131896

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta SAITO ,  Yuta KUROSU ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/12 ,  H01G4/248

Abstract: In a multilayer ceramic capacitor, a first segregation defined by at least one metal element selected from a group consisting of Mg, Mn, and Si is present at each of an end in a length direction of a first internal electrode layer not connected to a second external electrode and an end in a length direction of a second internal electrode layer not connected to a first external electrode. A second segregation defined by at least one metal element selected from a group consisting of Mg, Mn, and Si is present at each of an end of the first internal electrode layer in a width direction and an end of the second internal electrode layer in the width direction.

公开(公告)号：US20210202178A1

公开(公告)日：2021-07-01

申请号：US17131891

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008 ,  C04B35/468

Abstract: In a multilayer ceramic capacitor, an intersection of an interface is defined by a second dielectric ceramic layer, a first internal electrode layer or a second internal electrode layer, and a third dielectric ceramic layer, on a plane including a length direction and a width direction, the second dielectric ceramic layer and the third dielectric ceramic layer include a near intersection region at or near the intersection, and an average particle size of dielectric particles in the near intersection region is smaller than average particle sizes of dielectric particles in the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer.

公开(公告)号：US20180040426A1

公开(公告)日：2018-02-08

申请号：US15669044

申请日：2017-08-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro WAKASHIMA ,  Yuta SAITO ,  Kohei SHIMADA ,  Naobumi IKEGAMI

IPC: H01G4/248 ,  H01G4/12 ,  H05K1/18 ,  H01G4/30

CPC classification number: H01G4/248 ,  H01G2/06 ,  H01G4/1245 ,  H01G4/232 ,  H01G4/30 ,  H01G4/38 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/10015 ,  Y02P70/611

Abstract: An electronic component is able to be mounted on a mounting substrate including a pair of first edge portions that faces each other, and a pair of second edge portions that is perpendicular or substantially perpendicular to the pair of first edge portions and faces each other. The mounting substrate has a structure that allows at least any one of the electronic component, a first electronic component, and a second electronic component, to be mounted thereon. When a dimension of the first electronic component in a length direction is designated as L1, a dimension of the first electronic component in a width direction is designated as W1, a dimension of the second electronic component in the length direction is designated as L2, and a dimension of the second electronic component in the width direction is designated as W2, a dimension of the electronic component in the width direction is any one of W1 and W2. A dimension of the electronic component in the length direction is L2 when the dimension of the electronic component in the width direction is W1, and is L1 when the dimension of the electronic component in the width direction is W2.

公开(公告)号：US20240355552A1

公开(公告)日：2024-10-24

申请号：US18760090

申请日：2024-07-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Masahiro WAKASHIMA ,  Takefumi TAKAHASHI ,  Yuuta TAKAGI ,  Syouta IKEBE

IPC: H01G4/30 ,  H01G2/06 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1227

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated, and external electrodes each on a corresponding one of two end surfaces opposed to each other in a length direction perpendicular or substantially perpendicular to a lamination direction of the multilayer body. The external electrodes are each connected to the internal electrode layers. Each of the external electrodes includes a stack including a base electrode layer on a corresponding one of the two end surfaces, a Ni plated layer on the base electrode layer, and a Sn plated layer on the Ni plated layer. Each of the external electrodes includes a region in which Sn is deposited between the base electrode layer and the Ni plated layer.

公开(公告)号：US20240105391A1

公开(公告)日：2024-03-28

申请号：US18524673

申请日：2023-11-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/232 ,  H01G4/008 ,  H01G4/12 ,  H01G4/30

CPC classification number: H01G4/2325 ,  H01G4/008 ,  H01G4/1227 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, base electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers and each including glass and copper, and plated layers respectively provided on an outer side of the base electrode layers. A protective layer including sulfur is provided between the glass included in the base electrode layers and the plated layers.

公开(公告)号：US20230197340A1

公开(公告)日：2023-06-22

申请号：US18110396

申请日：2023-02-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki FUKUNAGA ,  Hideaki TANAKA ,  Masahiro WAKASHIMA ,  Daisuke HAMADA ,  Hironori TSUTSUMI ,  Satoshi MAENO ,  Ryota ASO ,  Koji MORIYAMA ,  Akihiro TSURU

IPC: H01G4/12 ,  H01G4/012 ,  H01G4/008 ,  H01G4/232 ,  H01G4/224

CPC classification number: H01G4/1227 ,  H01G4/012 ,  H01G4/0085 ,  H01G4/2325 ,  H01G4/224 ,  H01G4/30

Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.