公开(公告)号：US20170249981A1

公开(公告)日：2017-08-31

申请号：US15519851

申请日：2015-08-31

Applicant: NEC Corporation ,  TOHOKU UNIVERSITY

Inventor： Ryusuke NEBASHI ,  Noboru SAKIMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Hideo OHNO

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  G11C11/15 ,  H01L27/105 ,  H01L29/82

CPC classification number: G11C11/16 ,  G11C11/15 ,  G11C11/1675 ,  H01L27/105 ,  H01L27/222 ,  H01L29/82 ,  H01L43/08

Abstract: In order to stably write data into a magnetic memory that uses in-plane current-induced perpendicular switching of magnetization to write data, the magnetic memory includes a recording layer formed as a perpendicular magnetization film, an adjacent layer joined to an upper surface or a lower surface of the recording layer, an external magnetic field application part configured to apply a first external magnetic field to the recording layer in a first direction which is an in-plane direction of the recording layer, and a current application part configured to allow a write current to flow through the adjacent layer in the first direction or a second direction which is opposite to the first direction. The external magnetic field application part is configured to switch a direction of a second external magnetic field applied in a direction perpendicular to the first direction in accordance with a direction of the write current.

公开(公告)号：US20210081591A1

公开(公告)日：2021-03-18

申请号：US17054653

申请日：2019-05-14

Applicant: NEC Corporation

Inventor： Ayuka TADA ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ryusuke NEBASHI ,  Xu BAI

IPC: G06F30/3315

Abstract: A numerical information generating apparatus receives information of a programmable logic integrated circuit that includes a plurality of crossbar switches each including resistance change elements, calculates, for each of the plurality of crossbar switches, a base delay that is a delay in which influence of a load capacitance of other crossbar switch is excluded and a correction delay that is a delay caused by influence of a fanout of other crossbar switch, and further calculates a delay of each of the plurality of crossbar switches based on the base delay and the correction delay corresponding to each of the plurality of crossbar switches.

公开(公告)号：US20200380190A1

公开(公告)日：2020-12-03

申请号：US16766467

申请日：2018-11-21

Applicant: NEC Corporation

Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

IPC: G06F30/343 ,  G06F30/347

Abstract: A design assistance system including: a logic synthesis unit that receives input of an operation description file of the programmable logic integrated circuit, logically synthesizes the inputted operation description file, and generates a net list by using logic elements included in the programmable logic integrated circuit; an arrangement wiring unit that generates resource information of the programmable logic integrated circuit, arranges the logic elements included in the net list on the basis of the generated resource information, and virtually generates a signal path by laying wires among the arranged logic elements; and a reliability control unit that generates configuration information of the programmable logic integrated circuit on the basis of at least two reliability modes, and outputs the generated configuration information.

公开(公告)号：US20200336145A1

公开(公告)日：2020-10-22

申请号：US16957973

申请日：2019-01-21

Applicant: NEC Corporation

Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

IPC: H03K19/17736 ,  H03K19/17704 ,  H03K19/1776 ,  G11C13/00

Abstract: A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.

公开(公告)号：US20200168275A1

公开(公告)日：2020-05-28

申请号：US16611266

申请日：2017-05-12

Applicant: NEC Corporation

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Makoto MIYAMURA ,  Ayuka TADA ,  Ryusuke NEBASHI

IPC: G11C13/00 ,  H03K19/1776

Abstract: A reconfigurable circuit comprising: a complementary resistive switch; a write circuit to configure the complementary resistive switch; a read circuit to get ON/OFF information of the complementary resistive switch; a register to store ON/OFF information of the complementary resistive switch.

公开(公告)号：US20200145007A1

公开(公告)日：2020-05-07

申请号：US16621770

申请日：2017-08-10

Applicant: NEC Corporation

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Makoto MIYAMURA ,  Ayuka TADA ,  Ryusuke NEBASHI

IPC: H03K19/17736 ,  H03K19/173 ,  H03K19/17728

Abstract: A reconfigurable circuit comprising: crossbar switches; wires, each of which is coupled to one output port of one crossbar switch and input ports of the other crossbar switches; at least one inverter inserted on each wire for driving long-distance signal transfer, wherein one or less first inverter is inserted on the wire between two adjacent crossbar switches; one or two second inverters inserted between a crossbar switch input port and its connected wire.

公开(公告)号：US20190253057A1

公开(公告)日：2019-08-15

申请号：US16333317

申请日：2017-09-11

Applicant: NEC CORPORATION

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Ayuka TADA ,  Makoto MIYAMURA ,  Ryusuke NEBASHI

IPC: H03K19/177 ,  G11C13/00 ,  G06F17/50

Abstract: Provided is an integrated circuit that has reduced power consumption. The integrated circuit is provided with: a plurality of first wires one end of each of which is used as an input terminal; a plurality of second wires one end of each of which is used as an output terminal and which are respectively connected to the first wires; a bias wire which is connected to each of the second wires, and which is connected to a power supply or ground; a plurality of switches which connect the first wires or the bias wire and the second wires; and a selection circuit which selects electrical connection between the bias wire and the power supply or ground.

公开(公告)号：US20180302094A1

公开(公告)日：2018-10-18

申请号：US15767683

申请日：2015-10-16

Applicant: NEC Corporation

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Munehiro TADA ,  Yukihide TSUJI ,  Ayuka TADA ,  Makoto MIYAMURA ,  Ryusuke NEBASHI

IPC: H03K19/177 ,  G06F17/50 ,  G06F15/78

CPC classification number: H03K19/17756 ,  G06F15/7867 ,  G06F17/5054 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1776

Abstract: A reconfigurable circuit includes first and second wires and two or more paths active at different times. Each path includes: a first NVRS whose first terminal is connected to the first wire; a first transistor whose drain terminal is connected to a second terminal of the first NVRS; a second NVRS whose first terminal is connected to the second terminal of the first NVRS; a second transistor whose source terminal is connected to a second terminal of the second NVRS and whose drain terminal is connected to the second wire; and a 2-input AND circuit whose output is connected to a gate terminal of the first transistor. A time control signal is supplied to a first input of the 2-input AND circuit and a gate terminal of the second transistor. A write control signal is supplied to a second input of the 2-input AND circuit.