公开(公告)号：US09124644B2

公开(公告)日：2015-09-01

申请号：US13941494

申请日：2013-07-14

Applicant: Netronome Systems, Inc.

Inventor： Chirag P. Patel ,  Gavin J. Stark

IPC: H04L29/06 ,  G06F9/00

CPC classification number: H04L69/22 ,  G06F9/00 ,  G06F9/30018 ,  G06F9/3867 ,  H04L49/3063 ,  H04L69/04

Abstract: An egress packet modifier includes a script parser and a pipeline of processing stages. Rather than performing egress modifications using a processor that fetches and decodes and executes instructions in a classic processor fashion, and rather than storing a packet in memory and reading it out and modifying it and writing it back, the packet modifier pipeline processes the packet by passing parts of the packet through the pipeline. A processor identifies particular egress modifications to be performed by placing a script code at the beginning of the packet. The script parser then uses the code to identify a specific script of opcodes, where each opcode defines a modification. As a part passes through a stage, the stage can carry out the modification of such an opcode. As realized using current semiconductor fabrication process, the packet modifier can modify 200M packets/second at a sustained rate of up to 100 gigabits/second.

Abstract translation: 出口分组修饰符包括脚本解析器和处理阶段的流水线。 而不是使用处理器执行出口修改，处理器以经典处理器的方式获取和解码并执行指令，而不是将数据包存储在存储器中并将其读出并修改它并将其写回来，数据包修改器流水线通过传递来处理数据包 部分数据包通过管道。 处理器通过将脚本代码放置在分组的开始处来识别要执行的特定出口修改。 脚本解析器然后使用代码来识别操作码的特定脚本，其中每个操作码定义了一个修改。 作为一个阶段，舞台可以进行这样一个操作码的修改。 通过使用当前的半导体制造工艺实现，分组修改器可以以高达100吉比特/秒的持续速率修改200M分组/秒。

公开(公告)号：US20150169479A1

公开(公告)日：2015-06-18

申请号：US14631748

申请日：2015-02-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/287 ,  G06F7/10 ,  G06F9/34 ,  G06F9/467 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4234 ,  G06F17/30 ,  Y02D10/14 ,  Y02D10/151

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple key values from memory. Each key value is indicates a single RV to be output by the TM. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a key selector value. A key value is selected based upon the key selector value. A RV is selected based upon the key value. The key value is selected by a key selection circuit. The RV is selected by a result value selection circuit.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括存储器地址，起始位位置和掩码大小。 响应该命令，TM拉动输入值（IV）。 存储器地址用于从存储器读取包含多个结果值（RV）和多个键值的单词。 每个键值表示由TM输出的单个RV。 TM内的选择电路使用起始位位置和掩码大小来选择IV的一部分。 IV的部分是关键选择器值。 基于键选择器值选择键值。 基于键值选择RV。 键值由键选择电路选择。 RV由结果值选择电路选择。

公开(公告)号：US20150089242A1

公开(公告)日：2015-03-26

申请号：US14037319

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: H04L9/08

CPC classification number: G06F7/58

Abstract: An entropy storage ring includes an input node, a plurality of serial-connected stages, and an output node. Each stage includes an XOR (or XNOR) circuit, a delay element having an input coupled to the XOR output, and a combinatorial circuit having an output coupled to a second input of the XOR. The combinatorial circuit may be a NAND, NOR, AND or OR gate. A first input of the XOR is the data input of the stage. The output of the delay element is the data output of the stage. A first input of the combinatorial circuit is coupled to receive an enable bit from a configuration register. A second input of the combinatorial circuit is coupled to the ring output node. In operation, a bit stream is supplied onto the ring input node. Feedback of multiple stages are enabled so that the bit stream undergoes complex permutation as it circulates.

Abstract translation: 熵存储环包括输入节点，多个串联级和输出节点。 每个级包括XOR（或XNOR）电路，具有耦合到XOR输出的输入的延迟元件，以及具有耦合到XOR的第二输入的输出的组合电路。 组合电路可以是NAND，NOR，或或或门。 XOR的第一个输入是舞台的数据输入。 延迟元件的输出是级的数据输出。 组合电路的第一输入被耦合以从配置寄存器接收使能位。 组合电路的第二输入耦合到环形输出节点。 在操作中，位流被提供到环形输入节点上。 启用多级的反馈，使得位流在其循环时经历复杂的置换。

公开(公告)号：US20150089095A1

公开(公告)日：2015-03-26

申请号：US14037214

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/46 ,  G06F3/06

CPC classification number: G06F12/063 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F9/3004 ,  G06F9/3836 ,  G06F9/467 ,  G06F2212/251 ,  H04L45/74

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

Abstract translation: 事务存储器（TM）包括控制电路管线和相关联的存储器单元。 存储单元存储多个环。 对于每个环，流水线保持头指针和尾指针。 管道的环操作阶段将维护指针，因为值被放置在环上并被取消。 如果环未满，则put命令会使TM将值放入环中。 如果环不为空，则get命令使TM取环， 如果环具有至少预定量的可用缓冲空间，则具有低优先级命令的put将导致TM将值放入环中。 从一组ring命令获取，使TM从最高优先级非空环（指定的一组环）获取一个值。

公开(公告)号：US10911038B1

公开(公告)日：2021-02-02

申请号：US16247566

申请日：2019-01-15

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ronald N. Fortino

IPC: H03K17/00 ,  G06F13/40 ,  G06F9/46

Abstract: A network flow processor integrated circuit includes a plurality of processors, a plurality of multi-threaded transactional memories (MTMs), and a configurable mesh posted transaction data bus. The configurable mesh posted transaction data bus includes a configurable command mesh and a configurable data mesh. Each of these configurable meshes includes crossbar switches and interconnecting links. A command bus transaction value issued by a processor can pass across the command mesh to an MTM. The command bus transaction bus value includes a reference value. The MTM uses the reference value to pull data across the configurable data mesh into the MTM. The MTM then uses the data to carry out the commanded transactional memory operation. Multiple such commands can pass across the posted transaction bus across different parts of the integrated circuit at the same time, and a single MTM can be carrying out multiple such operations at the same time.

公开(公告)号：US10228968B2

公开(公告)日：2019-03-12

申请号：US15688937

申请日：2017-08-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Rolf Neugebauer

IPC: G06F9/46 ,  G06F13/38 ,  G06F12/109 ,  G06F12/1081

Abstract: A Network Interface Device (NID) of a web hosting server implements multiple virtual NIDs. For each virtual NID there is a block in a memory of a transactional memory on the NID. This block stores configuration information that configures the corresponding virtual NID. The NID also has a single managing processor that monitors configuration of the plurality of virtual NIDs. If there is a write into the memory space where the configuration information for the virtual NIDs is stored, then the transactional memory detects this write and in response sends an alert to the managing processor. The size and location of the memory space in the memory for which write alerts are to be generated is programmable. The content and destination of the alert is also programmable.

公开(公告)号：US10033638B1

公开(公告)日：2018-07-24

申请号：US14726438

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L29/06

Abstract: An integrated circuit includes a processor and an exact-match flow table structure. A first packet is received onto the integrated circuit. The packet is determined to be of a first type. As a result of this determination, execution by the processor of a first sequence of instructions is initiated. This execution causes bits of the first packet to be concatenated and modified in a first way, thereby generating a first Flow Id. The first Flow Id is an exact-match for the Flow Id of a first stored flow entry. A second packet is received. It is of a first type. As a result, a second sequence of instructions is executed. This causes bits of the second packet to be concatenated and modified in a second way, thereby generating a second Flow Id. The second Flow Id is an exact-match for the Flow Id of a second stored flow entry.

公开(公告)号：US09846662B2

公开(公告)日：2017-12-19

申请号：US14492015

申请日：2014-09-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark

IPC: G06F13/28 ,  G06F12/10 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F12/1081 ,  G06F13/1642 ,  G06F13/4027

Abstract: A chained Command/Push/Pull (CPP) bus command is output by a first device and is sent from a CPP bus master interface across a set of command conductors of a CPP bus to a second device. The chained CPP command includes a reference value. The second device decodes the command, in response determines a plurality of CPP commands, and outputs the plurality of CPP commands onto the CPP bus. The second device detects when the plurality of CPP commands have been completed, and in response returns the reference value back to the CPP bus master interface of the first device via a set of data conductors of the CPP bus. The reference value indicates to the first device that an overall operation of the chained CPP command has been completed.

公开(公告)号：US09830153B2

公开(公告)日：2017-11-28

申请号：US14311222

申请日：2014-06-20

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30069 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3802

Abstract: A pipelined run-to-completion processor executes a conditional skip instruction. If a predicate condition as specified by a predicate code field of the skip instruction is true, then the skip instruction causes execution of a number of instructions following the skip instruction to be “skipped”. The number of instructions to be skipped is specified by a skip count field of the skip instruction. In some examples, the skip instruction includes a “flag don't touch” bit. If this bit is set, then neither the skip instruction nor any of the skipped instructions can change the values of the flags. Both the skip instruction and following instructions to be skipped are decoded one by one in sequence and pass through the processor pipeline, but the execution stage is prevented from carrying out the instruction operation of a following instruction if the predicate condition of the skip instruction was true.

公开(公告)号：US09699107B2

公开(公告)日：2017-07-04

申请号：US14464690

申请日：2014-08-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Benjamin J. Cahill

IPC: G06F12/10 ,  H04L12/863 ,  H04L12/935 ,  H04L12/861 ,  H04L12/801 ,  H04L12/747

CPC classification number: H04L47/6245 ,  H04L45/742 ,  H04L47/35 ,  H04L47/621 ,  H04L49/3072 ,  H04L49/9063

Abstract: Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing and handling the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI (Packet Portion Identifier) Addressing Mode (PAM) in communicating with the packet engine and in instructing the packet engine to store packet portions. The packet engine uses linear memory addressing to write the packet portions into the memory, and to read the packet portions from the memory.