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48 条记录 (耗时 0.029 秒)

    Data programming circuit for programmable read only memory device
    21.
    发明授权
    Data programming circuit for programmable read only memory device 失效
    用于可编程只读存储器件的数据编程电路

    公开(公告)号：US4791612A

    公开(公告)日：1988-12-13

    申请号：US942895

    申请日：1986-12-17

    申请人： Masanobu Yoshida

    发明人： Masanobu Yoshida

    IPC分类号： G11C16/06 ,  G11C16/12 ,  G11C17/18 ,  G11C7/00

    CPC分类号： G11C16/12 ,  G11C16/06 ,  G11C17/18

    摘要： A programming circuit for a programmable read only memory device receiving a data signal to be programmed including a power supply terminal for receiving a first voltage in a read mode and a second voltage as a programming voltage which is a higher voltage than the first voltage in a program mode; an inverter circuit for converting an amplitude of the data signal in the program mode, the inverter including a load element and a first transistor having a drain connected to the load element and a gate receiving the data signal; and a switching circuit connected between the power source terminal and the load element for supplying the second voltage in the program mode and inhibiting a supply of the first voltage in the read mode.

    摘要翻译： 一种用于可编程只读存储器件的编程电路，用于接收要编程的数据信号，包括用于接收读取模式的第一电压的电源端子和作为比第一电压高的编程电压的第二电压 程序模式; 逆变器电路，用于在编程模式下转换数据信号的幅度，所述反相器包括负载元件和具有连接到所述负载元件的漏极的第一晶体管和接收所述数据信号的栅极; 以及连接在电源端子和负载元件之间的开关电路，用于在编程模式下提供第二电压，并且禁止在读取模式下提供第一电压。

    Decoder circuit having a variable power supply
    22.
    发明授权
    Decoder circuit having a variable power supply 失效
    解码电路具有可变电源

    公开(公告)号：US4782247A

    公开(公告)日：1988-11-01

    申请号：US759980

    申请日：1985-07-29

    申请人： Masanobu Yoshida

    发明人： Masanobu Yoshida

    IPC分类号： H01L27/00 ,  G11C16/08 ,  G11C16/12 ,  H03K19/017

    CPC分类号： G11C16/12 ,  G11C16/08

    摘要： A decoder circuit fabricated in an IC memory chip and provided to respective word-lines and respective bit-lines of an IC memory matrix fabricated in the IC memory chip, is provided for selecting an EPROM cell which is placed on an intersection point of the word-line and the bit-line, to program a datum into the EPROM cell by using a high power supply voltage when the decoder circuit operates under a programming mode and to read out a datum stored in the EPROM cell by using a low power supply voltage when the decoder circuit operates under a reading mode, receiving an address signal from the exterior of the decoder circuit. The decoder circuit comprises a NAND gate having its load and a CMOS invertor. In making the load of the NAND gate function as a constant current load, only a variable power supply voltage, which becomes a high and a low voltage according to the programming and the reading mode respectively, can be applied to the decoder circuit without using other elements such as a transfer gate and a compensator as required in the prior art.

    摘要翻译： 提供了一种在IC存储芯片中制造并提供给在IC存储器芯片中制造的IC存储器矩阵的各个字线和各个位线的解码器电路，用于选择放置在字的交点上的EPROM单元 线和位线，当解码器电路在编程模式下运行时，通过使用高电源电压将数据编程到EPROM单元中，并通过使用低电源电压读出存储在EPROM单元中的数据 当解码器电路在读取模式下操作时，从解码器电路的外部接收地址信号。 解码器电路包括具有负载的NAND门和CMOS反相器。 在使NAND门的负载作为恒定电流负载时，只有根据编程和读取模式分别成为高电平和低电压的可变电源电压可以被应用于解码器电路而不使用其他 诸如现有技术中所需的传输门和补偿器的元件。

    Data security device for storing data at a peripheral part of the device during power down thus preventing improper retrieval
    23.
    发明授权
    Data security device for storing data at a peripheral part of the device during power down thus preventing improper retrieval 失效
    用于在断电期间在设备的外围部分存储数据的数据安全设备，从而防止不正确的检索

    公开(公告)号：US4718038A

    公开(公告)日：1988-01-05

    申请号：US700176

    申请日：1985-02-11

    申请人： Masanobu Yoshida

    发明人： Masanobu Yoshida

    IPC分类号： G11C17/00 ,  G06F1/00 ,  G06F12/00 ,  G06F12/14 ,  G06F13/16 ,  G06F21/22 ,  G06F21/24 ,  G09C1/00 ,  G06F9/00

    CPC分类号： G06F12/1408

    摘要： A memory system having an erasable programmable read only memory (EPROM) for storing principal data, a read only memory (ROM) for storing key data, and a processing unit for writing or reading the principal data into or from the EPROM under control of the key data. The EPROM has an address converter having a volatile memory for temporarily storing the key data. External address data for wiring the principal data into the EPROM are converted to internal address data by the address converter using the key data stored in the volatile memory; the principal data stored in the EPROM are read out by converting external address data into internal address data, again using the key data stored in the volatile memory. The key data stored in the ROM are read out and applied to the volatile memory during the power turn-on of the memory system, the key data controlling the processing by the processing unit.

    摘要翻译： 一种存储系统，具有用于存储主数据的可擦除可编程只读存储器（EPROM），用于存储密钥数据的只读存储器（ROM），以及用于在主控制器的控制下将主数据写入或读取到EPROM的处理单元 关键数据。 EPROM具有地址转换器，具有用于临时存储密钥数据的易失性存储器。 用于将主数据连接到EPROM中的外部地址数据通过地址转换器使用存储在易失性存储器中的密钥数据转换成内部地址数据; 通过将外部地址数据转换为内部地址数据，再次使用存储在易失性存储器中的密钥数据来读出存储在EPROM中的主数据。 存储在ROM中的密钥数据在存储器系统的电源接通期间读出并应用于易失性存储器，该密钥数据控制处理单元的处理。

    Output circuit of a semiconductor device
    24.
    发明授权
    Output circuit of a semiconductor device 失效
    半导体器件的输出电路

    公开(公告)号：US4527077A

    公开(公告)日：1985-07-02

    申请号：US393551

    申请日：1982-06-30

    申请人： Mitsuo Higuchi ,  Masanobu Yoshida

    发明人： Mitsuo Higuchi ,  Masanobu Yoshida

    IPC分类号： G11C11/417 ,  G11C7/10 ,  H01L21/822 ,  H01L27/04 ,  H03K5/02 ,  H03K17/04 ,  H03K17/687 ,  H03K19/003 ,  H03K17/16 ,  H03K19/017

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K19/00315 ,  H03K19/00384 ,  H03K5/023 ,  G11C2207/108

    摘要： An output circuit of a semiconductor device for suppressing erroneous operation due to potential variations of the power supply line or the ground line. The output circuit comprises an output stage inverter connected between the power supply line and the ground line and a clamping circuit for clamping the voltages applied to the output stage inverter. A large instantaneous current which flows through the output stage inverter during a transition of state is greatly suppressed so that erroneous operation is prevented.

    摘要翻译： 一种用于抑制由于电源线或接地线的电位变化引起的误操作的半导体器件的输出电路。 输出电路包括连接在电源线和接地线之间的输出级反相器和用于钳位施加到输出级反相器的电压的钳位电路。 在状态转移期间流过输出级反相器的大的瞬时电流被大大抑制，从而防止错误操作。

    Medical X-ray imaging apparatus and X-ray detector for using the same
    27.
    发明授权
    Medical X-ray imaging apparatus and X-ray detector for using the same 有权
    医用X射线成像装置和X射线检测器

    公开(公告)号：US07577232B2

    公开(公告)日：2009-08-18

    申请号：US11407504

    申请日：2006-04-20

    申请人： Akifumi Tachibana ,  Masanobu Yoshida ,  Takahiro Yoshimura ,  Masakazu Suzuki

    发明人： Akifumi Tachibana ,  Masanobu Yoshida ,  Takahiro Yoshimura ,  Masakazu Suzuki

    IPC分类号： A61B6/14 ,  H05G1/58

    CPC分类号： A61B6/14 ,  G03B42/026

    摘要： An X-ray detector for use in a medical X-ray imaging apparatus comprising a rotary means rotatable relative to an object to be examined, an X-ray generator provided at one side of the rotary means, and an X-ray detecting portion provided at the other side of the rotary means so as to face the X-ray generator. The X-ray detector is provided in the X-ray detecting portion or is detachably mounted in the X-ray detecting portion, the X-ray detector is provided with an imaging portion comprised of a plane electric imaging means extending in a two-dimensional direction used for X-ray CT and has an imaging portion positioning means for moving up and down the imaging portion in the X-ray detector.

    摘要翻译： 一种用于医疗X射线成像装置的X射线检测器，包括相对于被检体可转动的旋转装置，设置在旋转装置的一侧的X射线发生器，以及X射线检测部， 在旋转装置的另一侧面对X射线发生器。 X射线检测器设置在X射线检测部分中或可拆卸地安装在X射线检测部分中，X射线检测器设置有成像部分，该成像部分包括平面电摄像装置，该平面电摄像装置以二维 用于X射线CT的方向，并且具有用于在X射线检测器中上下移动成像部分的成像部分定位装置。

    Semiconductor device with selectable device information
    28.
    发明授权
    Semiconductor device with selectable device information 失效
    具有可选设备信息的半导体器件

    公开(公告)号：US5701274A

    公开(公告)日：1997-12-23

    申请号：US466665

    申请日：1995-06-06

    申请人： Takao Akaogi ,  Masanobu Yoshida

    发明人： Takao Akaogi ,  Masanobu Yoshida

    IPC分类号： G11C17/00 ,  G11C5/00 ,  G11C5/14 ,  G11C16/02 ,  G11C16/06 ,  G11C16/20 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  G11C8/00

    CPC分类号： G11C5/145 ,  G11C16/20

    摘要： A semiconductor device has a function of reading device information specific to the device as and when required. The semiconductor device has storage units for storing plural pieces of device information and a selector for selecting a predetermined one of the information pieces stored in the storage units when a device information read mode is set, so that the read information may match device data such as a manufacturer name and part name printed on the semiconductor device.

    摘要翻译： 半导体器件具有在需要时读取器件特定信息的功能。 该半导体装置具有用于存储多条设备信息的存储单元和用于当设置设备信息读取模式时选择存储在存储单元中的预定的一个信息段的选择器，使得读取的信息可以匹配诸如 印刷在半导体器件上的制造商名称和部件名称。

    Nonvolatile semiconductor memory
    29.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US5490107A

    公开(公告)日：1996-02-06

    申请号：US996942

    申请日：1992-12-28

    申请人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    发明人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    IPC分类号： G11C16/26 ,  G11C16/30 ,  G11C29/04 ,  G11C11/34

    CPC分类号： G11C16/30 ,  G11C16/26 ,  G11C29/04 ,  G06F2201/81

    摘要： A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (V.sub.CC), the gate of the transistor being connected to a low source voltage (V.sub.ss) to provide an internal source voltage (V.sub.ci), a combination of an arrangement for dropping the external source voltage (V.sub.cc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (V.sub.pp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (V.sub.ref) as a lower threshold (V.sub.th) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (V.sub.ref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

    摘要翻译： 非易失性半导体存储器采用读出放大器，用于提供稳定的源极电压的电路和用于实现高速和可靠的读取和写入操作的电路。 半导体存储器具有非易失性可擦除存储单元晶体管的矩阵。 半导体存储器采用有效地使用多个源极电压并施加验证电压以读取放大器和字线的布置，用于检测读出放大器的输出的写入验证装置，用于将读出放大器的输出与 用于确定存储单元晶体管的写入状态是否可接受的参考值，用于响应于流向存储单元晶体管的电流，利用反相器和晶体管调整读出放大器的输出的装置，以改善 感测放大器的驱动速度，使用连接到外部源电压（VCC）的n沟道耗尽晶体管的内部源极电压产生装置，晶体管的栅极连接到低源电压（Vss）以提供内部源极 电压（Vci），用于将用于读取的外部源电压（Vcc）下降到预定值的装置的组合 驱动存储器中的读取电路和用于丢弃用于写入的外部电压（Vpp）的布置，以产生用于写入后验证操作的字线电位，用于将参考电压（Vref）设置为 允许单元晶体管（1100〜1122）的下限阈值（Vth），并将数据总线（13）的电压与参考电压（Vref）进行比较，以对所有存储单元晶体管同时执行擦除验证操作，以及 用于在读出放大器的读取时间期间访问下一个地址的预读布置，以提高读取速度。

    Nonvolatile semiconductor memory
    30.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US5487036A

    公开(公告)日：1996-01-23

    申请号：US268580

    申请日：1994-07-06

    申请人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    发明人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    IPC分类号： G11C16/26 ,  G11C16/30 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C16/30 ,  G11C16/26 ,  G11C29/04 ,  G06F2201/81

    摘要： A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (Vcc), the gate of the transistor being connected to a low source voltage (Vss) to provide an internal source voltage (Vci), a combination of an arrangement for dropping the external source voltage (Vcc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (Vref) as a lower threshold (Vth) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (Vref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

    摘要翻译： 非易失性半导体存储器采用读出放大器，用于提供稳定的源极电压的电路和用于实现高速和可靠的读取和写入操作的电路。 半导体存储器具有非易失性可擦除存储单元晶体管的矩阵。 半导体存储器采用有效地使用多个源极电压并施加验证电压以读取放大器和字线的布置，用于检测读出放大器的输出的写入验证装置，用于将读出放大器的输出与 用于确定存储单元晶体管的写入状态是否可接受的参考值，用于响应于流向存储单元晶体管的电流，利用反相器和晶体管调整读出放大器的输出的装置，以改善 读出放大器的驱动速度，使用连接到外部源极电压（Vcc）的n沟道耗尽晶体管的内部源极电压产生装置，晶体管的栅极连接到低电源电压（Vss）以提供内部源极 电压（Vci），用于将用于读取的外部源电压（Vcc）下降到预定值的装置的组合 驱动存储器中的读取电路和用于丢弃用于写入的外部电压（Vpp）的布置，以产生用于写入后验证操作的字线电位，用于将参考电压（Vref）设置为 允许单元晶体管（1100〜1122）的下限阈值（Vth），并将数据总线（13）的电压与参考电压（Vref）进行比较，以对所有存储单元晶体管同时执行擦除验证操作，以及 用于在读出放大器的读取时间期间访问下一个地址的预读布置，以提高读取速度。