公开(公告)号：US20160225749A1

公开(公告)日：2016-08-04

申请号：US15021393

申请日：2014-09-10

Applicant: OSRAM OPTO SEMICONDUCTORS GMBH

Inventor： Christian Leirer ,  Berthold Hahn ,  Roland Zeisel ,  Johannes Baur ,  Karl Engl

IPC: H01L25/16 ,  H01L33/48 ,  H01L33/62

CPC classification number: H01L25/167 ,  H01L25/0753 ,  H01L27/15 ,  H01L27/156 ,  H01L33/382 ,  H01L33/483 ,  H01L33/62 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2933/0016 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2224/4554

Abstract: An optoelectronic semiconductor chip includes a semiconductor layer sequence. The semiconductor layer sequence includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and an active zone having a p-n junction, which active zone is formed between the first semiconductor region and the second semiconductor region. The semiconductor layer sequence is arranged on a carrier. The semiconductor chip also includes a first contact, which is provided for electrically connecting the first semiconductor region, and a second contact, which is different from the first contact and which is provided for electrically connecting the second semiconductor region. In addition, the semiconductor chip includes a first capacitive electrical element, which is connected in parallel with the p-n junction and which has a first dielectric element.

Abstract translation: 光电半导体芯片包括半导体层序列。 半导体层序列包括第一导电类型的第一半导体区域，第二导电类型的第二半导体区域和具有p-n结的有源区，该有源区形成在第一半导体区域和第二半导体区域之间。 半导体层序列布置在载体上。 半导体芯片还包括第一触点，其设置用于电连接第一半导体区域，第二触点与第一触点不同，并且用于电连接第二半导体区域。 此外，半导体芯片包括与p-n结并联连接并具有第一介电元件的第一电容电元件。

公开(公告)号：US20150287883A1

公开(公告)日：2015-10-08

申请号：US14739684

申请日：2015-06-15

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Johannes Baur ,  Berthold Hahn ,  Volker Haerle ,  Karl Engl ,  Joachim Hertkorn ,  Tetsuya Taki

IPC: H01L33/32 ,  H01L33/46 ,  H01L33/50

CPC classification number: H01L33/32 ,  H01L21/02612 ,  H01L21/78 ,  H01L24/73 ,  H01L29/02 ,  H01L33/0079 ,  H01L33/08 ,  H01L33/46 ,  H01L33/507 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A composite substrate has a carrier and a utility layer. The utility layer is attached to the carrier by means of a dielectric bonding layer and the carrier contains a radiation conversion material. Other embodiments relate to a semiconductor chip having such a composite substrate, a method for producing a composite substrate and a method for producing a semiconductor chip with a composite substrate.

Abstract translation: 复合衬底具有载体和效用层。 实用层通过介电粘合层附着到载体上，载体包含辐射转换材料。 其他实施方式涉及具有这种复合基板的半导体芯片，复合基板的制造方法以及具有复合基板的半导体芯片的制造方法。

公开(公告)号：US20150053919A1

公开(公告)日：2015-02-26

申请号：US14526713

申请日：2014-10-29

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Nikolaus Gmeinwieser ,  Berthold Hahn

IPC: H01L33/50 ,  H01L33/32 ,  H01L33/06

CPC classification number: H01L33/508 ,  H01L33/06 ,  H01L33/08 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L33/504

Abstract: An optoelectronic semiconductor chip having a semiconductor layer sequence includes at least one active layer that generates primary radiation; a plurality of conversion layers that at least partially absorb the primary radiation and convert the primary radiation into secondary radiation of a longer wavelength than the primary radiation; and a roughened portion that extends at least into one of the conversion layers, wherein the roughened portion has a random structure, the semiconductor layer sequence is arranged on a carrier, a top side of the semiconductor layer sequence facing away from the carrier is formed by the roughened portion, the at least one active layer is located between the carrier and the conversion layers, and the roughened portion includes a plurality of recesses free of a semiconductor material.

Abstract translation: 具有半导体层序列的光电子半导体芯片包括产生初级辐射的至少一个有源层; 多个转换层，其至少部分地吸收主辐射并将主辐射转换成比主辐射更长波长的次级辐射; 以及至少延伸到一个转换层中的粗糙部分，其中粗糙部分具有随机结构，半导体层序列布置在载体上，半导体层序列的背离载体的顶侧由 所述粗糙部分，所述至少一个有源层位于所述载体和所述转换层之间，并且所述粗糙部分包括多个没有半导体材料的凹部。