公开(公告)号：US06714044B1

公开(公告)日：2004-03-30

申请号：US10106673

申请日：2002-03-25

申请人： Gopi Rangan ,  Khai Nguyen ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Yan Chong ,  Philip Pan ,  Joseph Huang ,  Bonnie Wang

发明人： Gopi Rangan ,  Khai Nguyen ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Yan Chong ,  Philip Pan ,  Joseph Huang ,  Bonnie Wang

IPC分类号： G06F738

CPC分类号： H03K19/17776 ,  G11C2207/104 ,  H03K19/17764

摘要： Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register is segmented into two or more segments, each segment being made up of a serial chain of registers (808). The configuration data is input into the two of more segments of the data registers in parallel. Circuitry is also provided to handle redundancy.

摘要翻译： 技术和电路用于更快速地配置可编程集成电路。 配置数据通过并行输入（705）并行输入到可编程集成电路中，并且该数据也在内部并行处理。 配置数据将被存储在数据寄存器（722）中。 该数据寄存器被分割成两个或多个段，每个段由串行链路寄存器（808）组成。 配置数据并行输入数据寄存器的两个更多段。 还提供电路来处理冗余。

公开(公告)号：US07098690B2

公开(公告)日：2006-08-29

申请号：US11025774

申请日：2004-12-29

申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： C07K16/28 ,  A61K2039/505 ,  C07K14/47

摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

摘要翻译： 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速I / O模式（如双数据速率和零总线周转）进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块为输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

公开(公告)号：US06246270B1

公开(公告)日：2001-06-12

申请号：US09345434

申请日：1999-07-01

申请人： Bonnie Wang ,  Joseph Huang ,  Wayne Yeung ,  Chiakang Sung ,  Richard Cliff ,  Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim

发明人： Bonnie Wang ,  Joseph Huang ,  Wayne Yeung ,  Chiakang Sung ,  Richard Cliff ,  Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim

IPC分类号： H03K426

CPC分类号： H03K17/04206 ,  H03K17/6871

摘要： Disclosed is a current booster or kicker for an output amplifier of a programmable logic control or other integrated circuit. The current booster includes a control mechanism and an auxiliary voltage supply. When a change in output state is initiated, the control mechanism connects the auxiliary voltage supply to the output of the output amplifier. After a change in output state in completed, the control mechanism disconnects the auxiliary voltage supply from the output of the output amplifier. In this way, the output amplifier can drive a relatively high capacitance load at a relatively high slew rate.

摘要翻译： 公开了用于可编程逻辑控制或其他集成电路的输出放大器的电流增压器或激光器。 电流增压器包括控制机构和辅助电压源。 当启动输出状态的变化时，控制机构将辅助电源连接到输出放大器的输出端。 在完成输出状态改变后，控制机构将输出放大器的输出端的辅助电源断开。 以这种方式，输出放大器可以以相对较高的转换速率驱动较高的电容负载。

公开(公告)号：US20050253626A1

公开(公告)日：2005-11-17

申请号：US11005890

申请日：2004-12-06

申请人： Yan Chong ,  Chiakang Sung ,  Bonnie Wang ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  In What Kim ,  Gopi Rangan ,  Tzung-Chin Chang ,  Surgey Shumarayev ,  Thomas White

发明人： Yan Chong ,  Chiakang Sung ,  Bonnie Wang ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  In What Kim ,  Gopi Rangan ,  Tzung-Chin Chang ,  Surgey Shumarayev ,  Thomas White

IPC分类号： G01R19/155 ,  G06F1/24 ,  G06F1/28 ,  G06F1/32 ,  H03K3/356 ,  H03K17/22 ,  H03K19/0175

CPC分类号： H03K3/356008 ,  G01R19/155 ,  G06F1/24 ,  G06F1/28 ,  G06F1/3203 ,  H03K17/223

摘要： A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.

公开(公告)号：US06535031B1

公开(公告)日：2003-03-18

申请号：US10146438

申请日：2002-05-13

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

IPC分类号： H03K522

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

公开(公告)号：US06400598B1

公开(公告)日：2002-06-04

申请号：US09843299

申请日：2001-04-25

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G. Cliff ,  Joseph Huang ,  Bonnie I. Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G. Cliff ,  Joseph Huang ,  Bonnie I. Wang ,  Wayne Yeung

IPC分类号： G11C506

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

摘要翻译： 可编程逻辑器件通过在器件上提供LVDS输入缓冲器和/或LVDS输出缓冲器来配备低电压差分信号（“LVDS”）。 对于LVDS成对使用的设备上的I / O引脚可以单独用于其他类型的信令。 尽管由于温度，制造过程不一致以及电源变化而导致变化，LVDS缓冲器也可以提供良好的性能和满足LVDS规范。

公开(公告)号：US06346827B1

公开(公告)日：2002-02-12

申请号：US09366937

申请日：1999-08-04

申请人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  In Whan Kim

发明人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  In Whan Kim

IPC分类号： H01L2500

CPC分类号： G11C5/147 ,  G11C5/066

摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

摘要翻译： 可编程逻辑器件输入/输出引脚的可编程输入/输出电路可以在标准I / O模式或参考电压模式下进行配置。 该电路包括可跟踪的标准I / O缓冲器以及参考电压钳位电路。 在参考电压模式下，I / O电路被三态化，参考电压钳位电路将参考电压从I / O引脚传递到参考电压总线。 在标准I / O模式下，I / O缓冲区可以运行。 参考电压钳位电路将I / O引脚与参考电压总线隔离，并可能包括欠压和过压保护，以防止参考电压总线受到超出范围I / O信号的干扰。

公开(公告)号：US07196556B1

公开(公告)日：2007-03-27

申请号：US10350551

申请日：2003-01-22

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G Cliff ,  Joseph Huang ,  Bonnie I Wang ,  Wayne Yeung

IPC分类号： H03K3/00

CPC分类号： H03K3/35613 ,  H03K19/018528 ,  H04L25/0272

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

摘要翻译： 可编程逻辑器件通过在器件上提供LVDS输入缓冲器和/或LVDS输出缓冲器来配备低电压差分信号（“LVDS”）。 对于LVDS成对使用的设备上的I / O引脚可以单独用于其他类型的信令。 尽管由于温度，制造过程不一致以及电源变化而导致变化，LVDS缓冲器也可以提供良好的性能和满足LVDS规范。

公开(公告)号：US06836164B1

公开(公告)日：2004-12-28

申请号：US10702300

申请日：2003-11-05

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

IPC分类号： H03L706

CPC分类号： H03K19/1774 ,  H03K23/665 ,  H03K2005/00045 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/0997 ,  H03L7/183

摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

摘要翻译： 电路提供可编程相移特征，其中相移可由用户可编程地选择。 该电路可以并入可编程逻辑器件（PLD）或现场可编程门阵列（FPGA）中，以提供额外的可编程特性。 可编程相移电路可以在锁相环（PLL）或延迟锁定环（DLL）电路内实现。

公开(公告)号：US06369624B1

公开(公告)日：2002-04-09

申请号：US09432142

申请日：1999-11-02

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Xiaobao Wang ,  In Whan Kim ,  Wayne Yeung ,  Khai Nguyen

IPC分类号： H03L706

CPC分类号： H03K19/1774 ,  H03K23/665 ,  H03K2005/00045 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/0997 ,  H03L7/183

摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

摘要翻译： 电路提供可编程相移特征，其中相移可由用户可编程地选择。 该电路可以并入可编程逻辑器件（PLD）或现场可编程门阵列（FPGA）中，以提供额外的可编程特性。 可编程相移电路可以在锁相环（PLL）或延迟锁定环（DLL）电路内实现。