公开(公告)号：US09190405B2

公开(公告)日：2015-11-17

申请号：US14169592

申请日：2014-01-31

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Ohsang Kwon ,  Satyanarayana Sahu ,  Divya Gangadharan ,  Chih-Iung Kao ,  Renukprasad Shreedhar Hiremath ,  Animesh Datta ,  Qi Ye

IPC: H01L27/00 ,  H01L27/088 ,  H01L29/06 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L27/088 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0653 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.

Abstract translation: 包括标准单元的CMOS器件包括在第一和第二晶体管之间具有栅极的第一和第二晶体管。 一个有源区域在第一和第二晶体管之间以及栅极之下延伸。 在第一种配置中，当栅极侧面的第一和第二晶体管的漏极/源极具有相同的信号时，漏极/源极连接在一起并连接到栅极。 在第二配置中，当栅极侧的第一晶体管的源极连接到源极电压时，栅极另一侧的第二晶体管的漏极/源极传送信号时，第一晶体管的源极 连接到门。 在第三种配置中，当栅极侧面的第一和第二晶体管的源极连接到源极电压时，栅极浮动。

公开(公告)号：US20140359385A1

公开(公告)日：2014-12-04

申请号：US13905060

申请日：2013-05-29

Applicant: QUALCOMM INCORPORATED

Inventor： Jay Madhukar Shah ,  Chethan Swamynathan ,  Animesh Datta

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318541

Abstract: Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

Abstract translation: 本文描述了用于减少可扫描的翻转托盘中的扫描开销的技术。 在一个实施例中，用于翻转托盘的扫描电路包括三态电路，其被配置为反转输入数据信号，并将反相数据信号以正常模式输出到翻转托盘的触发器的输入，并阻塞 来自触发器的输入的扫描模式的数据信号。 扫描电路还包括一个通道门，其被配置为在扫描模式下将扫描信号传递到触发器的输入，并且在正常模式下阻止来自触发器的输入的扫描信号。

公开(公告)号：US11437375B2

公开(公告)日：2022-09-06

申请号：US16744227

申请日：2020-01-16

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L23/535 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/482 ,  H03K17/687 ,  H03K17/16 ,  H01L23/522

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US10580774B2

公开(公告)日：2020-03-03

申请号：US16057036

申请日：2018-08-07

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L21/8238 ,  H03K17/16 ,  H03K17/687 ,  H01L23/482 ,  H01L27/02 ,  H01L23/535 ,  H01L23/522

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US10033359B2

公开(公告)日：2018-07-24

申请号：US14921341

申请日：2015-10-23

Applicant: QUALCOMM Incorporated

Inventor： Qi Ye ,  Animesh Datta

IPC: H03K3/037 ,  H03K3/356 ,  H03K3/3562

Abstract: A method and an apparatus for wireless communication are provided. The apparatus having a first latch having a first latch input and first latch output and a second latch having a second latch input, a second latch scan output, and a second latch data output. The second latch input is coupled to the first latch output. The apparatus further includes a selection component configured to select between a data input and a scan input based on a shift input. The selection component is coupled to the first latch input. The selection component includes a first NAND-gate, a second NAND-gate, and an OR-gate.

公开(公告)号：US09966953B2

公开(公告)日：2018-05-08

申请号：US15171487

申请日：2016-06-02

Applicant: QUALCOMM Incorporated

Inventor： Qi Ye ,  Animesh Datta ,  Bo Pang

IPC: H03K3/037 ,  H03K19/21 ,  H03K19/00

CPC classification number: H03K19/0016 ,  H03K3/012 ,  H03K3/037 ,  H03K19/21

Abstract: A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.

公开(公告)号：US09659936B2

公开(公告)日：2017-05-23

申请号：US13975074

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/482 ,  H01L27/02 ,  H03K17/16 ,  H03K17/687 ,  H01L23/522

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

公开(公告)号：US09318476B2

公开(公告)日：2016-04-19

申请号：US14195525

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Animesh Datta ,  Seid Hadi Rasouli

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11831 ,  H01L2027/11861 ,  H01L2027/11866

Abstract: A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.

Abstract translation: 提供晶体管单元，其包括覆盖连续氧化物定义（OD）区域的虚拟栅极。 与虚设的第一侧相邻的OD区域的第一部分形成漏极。 单元包括局部互连结构，其将虚拟栅极和邻近伪栅极的第二相对侧的OD区域的一部分耦合到源极电压。

公开(公告)号：US09083325B2

公开(公告)日：2015-07-14

申请号：US13918670

申请日：2013-06-14

Applicant: QUALCOMM Incorporated

Inventor： Animesh Datta ,  Qi Ye ,  Chih-Lung Kao

IPC: G06F7/38 ,  G05B19/045 ,  H03K3/037 ,  H03K3/29

CPC classification number: H03K3/0375 ,  G05B19/045 ,  H03K3/037 ,  H03K3/29

Abstract: Techniques for fixing hold violations using metal-programmable cells are described herein. In one embodiment, a system comprises a first flip-flop, a second flip-flop, and a data path between the first and second flip-flops. The system further comprises a metal-programmable cell connected to the data path, wherein the metal-programmable cell is programmed to implement at least one capacitor to add a capacitive load to the data path. The capacitive load adds delay to the data path that prevents a hold violation at one of the first and second flip-flops.

Abstract translation: 本文描述了使用金属可编程单元固定保持违规的技术。 在一个实施例中，系统包括第一触发器，第二触发器和第一和第二触发器之间的数据通路。 该系统还包括连接到数据路径的金属可编程单元，其中该金属可编程单元被编程为实现至少一个电容器以向该数据路径添加电容性负载。 容性负载增加数据通路的延迟，防止在第一和第二触发器之一处的保持违反。

公开(公告)号：US20140368247A1

公开(公告)日：2014-12-18

申请号：US13918670

申请日：2013-06-14

Applicant: QUALCOMM Incorporated

Inventor： Animesh Datta ,  Qi Ye ,  Chih-Lung Kao

IPC: H03K3/356

CPC classification number: H03K3/0375 ,  G05B19/045 ,  H03K3/037 ,  H03K3/29

Abstract: Techniques for fixing hold violations using metal-programmable cells are described herein. In one embodiment, a system comprises a first flip-flop, a second flip-flop, and a data path between the first and second flip-flops. The system further comprises a metal-programmable cell connected to the data path, wherein the metal-programmable cell is programmed to implement at least one capacitor to add a capacitive load to the data path. The capacitive load adds delay to the data path that prevents a hold violation at one of the first and second flip-flops.

Abstract translation: 本文描述了使用金属可编程单元固定保持违规的技术。 在一个实施例中，系统包括第一触发器，第二触发器和第一和第二触发器之间的数据通路。 该系统还包括连接到数据路径的金属可编程单元，其中该金属可编程单元被编程为实现至少一个电容器以向该数据路径添加电容性负载。 容性负载增加数据通路的延迟，防止在第一和第二触发器之一处的保持违反。