公开(公告)号：US08600754B2

公开(公告)日：2013-12-03

申请号：US13647868

申请日：2012-10-09

Applicant: Qualcomm Incorporated

Inventor： Bohuslav Rychlik

IPC: G10L13/00 ,  G10L11/02 ,  G01C21/00

CPC classification number: G01C21/3629 ,  H04M1/72525 ,  H04M2250/10

Abstract: Various embodiments of methods and systems for providing informational updates, such as directional updates, to a user of a computing device are disclosed. The method and system may recognize an active conversation and monitor the conversation for a lull. During a detected lull, the method and system may deliver the informational updates. Certain embodiments may include receiving a voice update while the user is using other functionality of the computing device, such as a telecommunication function. Embodiments may also include scheduling an update window within which the update may be delivered. The update window may be a predetermined time window in which a voice update is broadcast, for example. Embodiments may also include alerting the user to a pending update.

Abstract translation: 公开了用于向计算设备的用户提供诸如定向更新之类的信息更新的方法和系统的各种实施例。 该方法和系统可以识别活跃的对话并且监视对话以进行暂停。 在检测到的延迟期间，该方法和系统可以传递信息更新。 某些实施例可以包括在用户正在使用诸如电信功能的计算设备的其他功能之间接收语音更新。 实施例还可以包括调度其中可以传送更新的更新窗口。 更新窗口可以是例如广播语音更新的预定时间窗口。 实施例还可以包括提醒用户进行待定更新。

公开(公告)号：US20130074085A1

公开(公告)日：2013-03-21

申请号：US13669043

申请日：2012-11-05

Applicant: Qualcomm Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman S. Gargash

IPC: G06F1/08 ,  G06F9/46

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案，方案，系统和设备，配置为计算和实施性能保证，以确保处理器不处于忙碌状态（例如，由于临时工作负载）超过预定量 的时间高于该处理器完成其预先计算的稳态工作负载所需的时间。 DCVS可以基于可变延迟来调整处理器的频率和/或电压，以确保处理核心仅在最大程度上预定的最大工作量之下落在其稳态工作负载之后，而与工作频率或电压无关 的处理器。

公开(公告)号：US11636057B2

公开(公告)日：2023-04-25

申请号：US17390215

申请日：2021-07-30

Applicant: QUALCOMM INCORPORATED

Inventor： Engin Ipek ,  Bohuslav Rychlik ,  George Patsilaras ,  Prajakt Kulkarni ,  Can Hankendi ,  Fahad Ali ,  Jeffrey Gemar ,  Matthew Severson

IPC: G06F13/16 ,  H03M5/14

Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.

公开(公告)号：US20200250097A1

公开(公告)日：2020-08-06

申请号：US16269440

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： WESLEY JAMES HOLLAND ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  George Patsilaras ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06F12/0862 ,  G06F12/1009 ,  G06T1/60

Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

公开(公告)号：US20180081809A1

公开(公告)日：2018-03-22

申请号：US15268791

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/0817 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/0828 ,  G06F3/0613 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0835 ,  G06F13/1663 ,  G06F13/4022 ,  G06F2212/621 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing a hybrid input/output (I/O) coherent write request on a computing device, including receiving an I/O coherent write request, generating a first hybrid I/O coherent write request and a second hybrid I/O coherent write request from the I/O coherent write request, sending the first hybrid I/O coherent write request and I/O coherent write data of the I/O coherent write request to a shared memory, and sending the second hybrid I/O coherent write request without the I/O coherent write data of the I/O coherent write request to a coherency domain.

公开(公告)号：US09846612B2

公开(公告)日：2017-12-19

申请号：US14823879

申请日：2015-08-11

Applicant: QUALCOMM INCORPORATED

Inventor： Madan Krishnappa ,  Chinh Tran ,  Li Zhang ,  Alan Young ,  William Bainbridge ,  Bohuslav Rychlik

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11 ,  G06F1/32 ,  G06F11/30 ,  G11B20/18

CPC classification number: G06F11/10 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/3058 ,  G06F11/3062 ,  G11B20/1816 ,  H03M13/11 ,  H03M13/611 ,  H03M13/6505 ,  Y02D10/172

Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

公开(公告)号：US09684787B2

公开(公告)日：2017-06-20

申请号：US14247400

申请日：2014-04-08

Applicant: QUALCOMM Incorporated

Inventor： Vinay Sridhara ,  Rajarshi Gupta ,  Bohuslav Rychlik

IPC: G06F21/56 ,  G06F9/48 ,  G06F1/32

CPC classification number: G06F21/566 ,  G06F1/3206 ,  G06F9/4893

Abstract: Methods, systems and devices compute and use the actual execution states of software applications to implement power saving schemes and to perform behavioral monitoring and analysis operations. A mobile device may be configured to monitor an activity of a software application, generate a shadow feature value that identifies actual execution state of the software application during that activity, generate a behavior vector that associates the monitored activity with the shadow feature value, and determine whether the activity is malicious or benign based on the generated behavior vector, shadow feature value and/or operating system execution states. The mobile device processor may also be configured to intelligently determine whether the execution state of a software application is relevant to determining whether any of the monitored mobile device behaviors are malicious or suspicious, and monitor only the execution states of the software applications for which such determinations are relevant.

公开(公告)号：US09612971B2

公开(公告)日：2017-04-04

申请号：US14462763

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/0866 ,  G06F12/0886 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0893 ,  G06F12/0866 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by writing supplemental data to the unfilled portions of the cache line. A cache memory controller may receive a cache memory access request with a supplemental write command for data smaller than a cache line. The cache memory controller may write supplemental to the portions of the cache line not filled by the data in response to a write cache memory access request or a cache miss during a read cache memory access request. In the event of a cache miss, the cache memory controller may retrieve the data from the main memory, excluding any overfetch data, and write the data and the supplemental data to the cache line. Eliminating overfetching reduces bandwidth and power required to retrieved data from main memory.

公开(公告)号：US20160203084A1

公开(公告)日：2016-07-14

申请号：US15077534

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

Abstract translation: 用于在高速缓存的高速缓存行中压缩数据的方法，设备和非暂态过程可读存储介质。 方面方法可以包括由计算设备的处理器识别用于第一数据段的基地址（例如，物理或虚拟高速缓存地址），识别第一数据段的数据大小（例如，基于压缩比） 数据段，基于所识别的数据大小和第一数据段的基址获得基本偏移，并且通过利用所获得的基本偏移量偏移基址来计算偏移地址，其中所计算的偏移地址与第二数据相关联 分割。 在一些方面，所述方法可以包括基于所述基地址识别所述第一数据段的奇偶校验值，并通过使用所识别的数据大小和所识别的奇偶校验值对存储的表执行查找来获得所述基本偏移。

公开(公告)号：US09355038B2

公开(公告)日：2016-05-31

申请号：US14483902

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/06 ,  G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0886 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an aspect, cache bank spreading may include determining whether the compressed data of the cache memory access fits on a single cache bank. In response to determining that the compressed data fits on a single cache bank, a cache bank spreading value may be calculated to replace/reinstate bank selection bits of the physical address for a cache memory of the cache memory access request that may be cleared during data compression. A cache bank spreading address in the physical space of the cache memory may include the physical address of the cache memory access request plus the reinstated bank selection bits. The cache bank spreading address may be used to read compressed data from or write compressed data to the cache memory device.

Abstract translation: 方面包括计算设备，系统和方法，用于使用高速缓存存储体扩展来实现用于压缩数据的高速缓存存储器访问请求。 在一方面，高速缓存存储体扩展可以包括确定高速缓冲存储器访问的压缩数据是否适合于单个高速缓存存储体。 响应于确定压缩数据适合于单个高速缓存存储体，可以计算高速缓存存储体扩展值以代替/恢复可以在数据期间清除的高速缓冲存储器访问请求的高速缓冲存储器的物理地址的存储体选择位 压缩。 高速缓冲存储器的物理空间中的高速缓存存储体扩展地址可以包括高速缓冲存储器访问请求的物理地址加上恢复的存储体选择位。 缓存存储体扩展地址可用于从压缩数据读取压缩数据或将压缩数据写入缓存存储器件。