公开(公告)号：US09318165B2

公开(公告)日：2016-04-19

申请号：US14218691

申请日：2014-03-18

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Rui Li ,  Sei Seung Yoon ,  Gregory Ameriada Uvieghara

IPC: H03F3/45 ,  G11C7/06 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C7/062 ,  G11C17/16 ,  G11C17/18 ,  H03F3/45183 ,  H03F3/45497 ,  H03F2203/45402 ,  H03F2203/45604 ,  H03F2203/45641 ,  H03F2203/45652

Abstract: A sense amplifier is disclosed that includes an amplifier circuit configured to receive, at an input, an input signal including an input level, the amplifier circuit configured to provide an amplified output signal including a gain with respect to the input level; and a feedback circuit coupled to receive the amplified output signal from the amplifier circuit, the feedback circuit configured to provide, at the input of the amplifier circuit, an adjusted version of the amplified output signal including a modified output magnitude based on common mode feedback.

Abstract translation: 公开了一种读出放大器，其包括放大器电路，其被配置为在输入端接收包括输入电平的输入信号，放大器电路被配置为提供包括相对于输入电平的增益的放大输出信号; 以及反馈电路，其耦合以从放大器电路接收放大的输出信号，所述反馈电路被配置为在放大器电路的输入处提供包括基于共模反馈的修改的输出幅度的经放大的输出信号的调整版本。

公开(公告)号：US20150029778A1

公开(公告)日：2015-01-29

申请号：US13953511

申请日：2013-07-29

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung Yoon ,  Chulmin Jung ,  Esin Terzioglu ,  Steven Millendorf

IPC: G11C17/12

CPC classification number: G11C17/12 ,  G11C7/24

Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word liens. Each memory cell includes a high Vt transistor and a low Vt transistor.

Abstract translation: 掩模编程的只读存储器（MROM）具有多个列线对，每一列具有位线和补码位线。 MROM包括与列线对和多个字留置权之间的多个交点相对应的多个存储单元。 每个存储单元包括高Vt晶体管和低Vt晶体管。

公开(公告)号：US20140269104A1

公开(公告)日：2014-09-18

申请号：US13837874

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Chulmin Jung

IPC: G11C7/08

CPC classification number: G11C7/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28 ,  G11C29/702 ,  G11C29/848

Abstract: A memory includes a redundant sense amplifier and a plurality of sense amplifier pairs. Each sense amplifier pair includes a first sense amplifier and a second sense amplifier. Each sense amplifier pair drives a common load line. The memory is configured to implement column redundancy using a single redundant sense amplifier without requiring local read lines for each sense amplifier.

Abstract translation: 存储器包括冗余读出放大器和多个读出放大器对。 每个读出放大器对包括第一读出放大器和第二读出放大器。 每个读出放大器对驱动公共负载线。 存储器被配置为使用单个冗余读出放大器实现列冗余，而不需要每个读出放大器的本地读取线。

公开(公告)号：US20140266398A1

公开(公告)日：2014-09-18

申请号：US13799686

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu ,  Hari Ananthanarayanan ,  Venugopal Boynapalli

IPC: H03K17/00

CPC classification number: H03K17/002 ,  G11C7/02 ,  G11C7/10 ,  G11C7/1006

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract translation: 本发明提供一种半导体装置，用于在半导体装置中的第一装置和第二装置之间传输数据时降低功率。 向半导体装置添加附加电路以创建通信系统，该通信系统减少用于所有通信的第一设备和第二设备之间的数据总线的每个信号线的状态变化的数量。 附加电路包括解码器，其耦合以接收和转换来自第一设备的值，用于通过数据总线传输到向第二设备提供值的恢复（即重新编码）版本的编码器。 一个或多个多路复用器也可以包括在附加电路中以支持任何数量的设备。

公开(公告)号：US11935606B2

公开(公告)日：2024-03-19

申请号：US17364738

申请日：2021-06-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Sahu ,  Sharad Kumar Gupta ,  Jung Pill Kim ,  Chulmin Jung ,  Jais Abraham

IPC: G11C29/10 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C29/10 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1096

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

公开(公告)号：US11894050B2

公开(公告)日：2024-02-06

申请号：US17481601

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Anil Chowdary Kota ,  Dhvani Sheth ,  Chulmin Jung

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

公开(公告)号：US10831667B2

公开(公告)日：2020-11-10

申请号：US16173221

申请日：2018-10-29

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar Rangarajan ,  Chulmin Jung ,  Rakesh Misra

IPC: G06F12/0846 ,  G06F12/0808 ,  G06F12/0891 ,  G06F12/0895

Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for accessing tag information in a memory line. The techniques include determining an operation to perform on at least one memory line of a memory. The techniques further include performing the operation by accessing only a portion of the at least one memory line, wherein the only the portion of the at least one memory line comprises one or more flag bits that are independently accessible from remaining bits of the at least one memory line.

公开(公告)号：US10748641B2

公开(公告)日：2020-08-18

申请号：US15964050

申请日：2018-04-26

Applicant: QUALCOMM Incorporated

Inventor： Greg Seok ,  Fahad Ahmed ,  Chulmin Jung

IPC: G11C29/44 ,  G11C29/10 ,  G11C29/18 ,  G11C29/16 ,  G11C29/50 ,  G11C29/26 ,  G11C29/04 ,  G11C29/38

Abstract: A method and apparatus for memory built-in self-test (MBIST) may be configured to load a testing program from an MBIST controller, execute the testing program, and determine and write pass/fail results to a read-out register. For example, in various embodiments, the testing program may comprise one or more write operations that are configured to change data stored in a plurality of memory bitcells from a first value to a second value while a byte enable signal is asserted in order to test stability associated with a memory bitcell, create DC and AC noise due to byte enable mode stress, check at-speed byte enable mode timing, and execute a self-checking algorithm that may be designed to verify whether data is received at a data input (Din) pin. Any memory bitcells storing a value different from an expected value after performing the write operation(s) may be identified as having failed the MBIST.

公开(公告)号：US10049729B1

公开(公告)日：2018-08-14

申请号：US15708393

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Sei Seung Yoon ,  Chulmin Jung ,  Bin Liang

IPC: G11C11/00 ,  G11C11/419

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a first voltage to a second voltage while the assist circuit is in a first state. The apparatus may also maintain the device operating voltage at the second voltage for a predetermined time. The apparatus may switch the assist circuit from the first state to a second state. The apparatus may adjust the device operating voltage to a third voltage after the predetermined time, wherein the second voltage is a voltage level between the first voltage and the third voltage. By transitioning the device operating voltage from the first voltage to the third voltage while at the same time preventing the assist circuit from entering particular read assist states, the apparatus may reduce a likelihood of read failures.

公开(公告)号：US20160299517A1

公开(公告)日：2016-10-13

申请号：US14684128

申请日：2015-04-10

Applicant: QUALCOMM Incorporated

Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

IPC: G05F1/10

CPC classification number: G05F1/10 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3287 ,  G06F1/329 ,  H02M1/32

Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.

Abstract translation: 公开了电压下降控制。 一种设备包括耦合到外部电源的第一组件和耦合到外部电源的第二组件。 第一组件包括被配置为接收第一电压的第一输入，被配置为响应于对应于第一逻辑值的第一电压由外部电源充电的第一内部电源;以及电压下降控制器，被配置为输出 经由第一输出的第二电压。 响应于满足第二电压电平的第一内部电源的第一电压电平，第二电压对应于第一逻辑值。 第二组件包括被配置为从第一输出接收第二电压的第二输入。